Jason Lowe-Power has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17870 )
Change subject: learning_gem5: Fix vector port panic in SimpleCache
......................................................................
learning_gem5: Fix vector port panic in SimpleCache
Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870
Reviewed-by: Anthony Gutierrez <anthony.gutier...@amd.com>
---
M src/learning_gem5/part2/simple_cache.cc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Anthony Gutierrez: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/learning_gem5/part2/simple_cache.cc
b/src/learning_gem5/part2/simple_cache.cc
index 880dc39..6deefde 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -54,10 +54,10 @@
Port &
SimpleCache::getPort(const std::string &if_name, PortID idx)
{
- panic_if(idx != InvalidPortID, "This object doesn't support vector
ports");
-
// This is the name from the Python SimObject declaration in
SimpleCache.py
if (if_name == "mem_side") {
+ panic_if(idx != InvalidPortID,
+ "Mem side of simple cache not a vector port");
return memPort;
} else if (if_name == "cpu_side" && idx < cpuPorts.size()) {
// We should have already created all of the ports in the
constructor
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Gerrit-Change-Number: 17870
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Anthony Gutierrez <anthony.gutier...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-MessageType: merged
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