Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/20251
to review the following change.
Change subject: arch-arm: Replace direct use cpsr.el with currEL helper
......................................................................
arch-arm: Replace direct use cpsr.el with currEL helper
The patch is replacing it in places where the current EL could be using
AArch32, hence leading to an incorrect ExceptionLevel.
Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/faults.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/interrupts.cc
M src/arch/arm/utility.cc
4 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0f279fa..ba51519 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1014,7 +1014,7 @@
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
- toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+ toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
return toHyp;
}
@@ -1536,7 +1536,7 @@
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
- toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+ toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
return toHyp;
}
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index ec70590..03a758f 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -686,7 +686,7 @@
ArmStaticInst::checkFPAdvSIMDEnabled64(ThreadContext *tc,
CPSR cpsr, CPACR cpacr) const
{
- const ExceptionLevel el = (ExceptionLevel) (uint8_t)cpsr.el;
+ const ExceptionLevel el = currEL(tc);
if ((el == EL0 && cpacr.fpen != 0x3) ||
(el == EL1 && !(cpacr.fpen & 0x1)))
return advSIMDFPAccessTrap64(EL1);
@@ -876,19 +876,21 @@
bool isWfe) const
{
Fault fault = NoFault;
- if (cpsr.el == EL0) {
+ ExceptionLevel curr_el = currEL(tc);
+
+ if (curr_el == EL0) {
fault = checkForWFxTrap32(tc, EL1, isWfe);
}
if ((fault == NoFault) &&
ArmSystem::haveEL(tc, EL2) && !inSecureState(scr, cpsr) &&
- ((cpsr.el == EL0) || (cpsr.el == EL1))) {
+ ((curr_el == EL0) || (curr_el == EL1))) {
fault = checkForWFxTrap32(tc, EL2, isWfe);
}
if ((fault == NoFault) &&
- ArmSystem::haveEL(tc, EL3) && cpsr.el != EL3) {
+ ArmSystem::haveEL(tc, EL3) && curr_el != EL3) {
fault = checkForWFxTrap32(tc, EL3, isWfe);
}
@@ -899,9 +901,9 @@
ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
{
bool setend_disabled(false);
- ExceptionLevel pstateEL = (ExceptionLevel)(uint8_t)(cpsr.el);
+ ExceptionLevel pstate_el = currEL(tc);
- if (pstateEL == EL2) {
+ if (pstate_el == EL2) {
setend_disabled =
((SCTLR)tc->readMiscRegNoEffect(MISCREG_HSCTLR)).sed;
} else {
// Please note: in the armarm pseudocode there is a distinction
@@ -923,7 +925,7 @@
setend_disabled =
((SCTLR)tc->readMiscRegNoEffect(banked_sctlr)).sed;
}
- return setend_disabled ? undefinedFault32(tc, pstateEL) :
+ return setend_disabled ? undefinedFault32(tc, pstate_el) :
NoFault;
}
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc
index 3d841e9..e2febb3 100644
--- a/src/arch/arm/interrupts.cc
+++ b/src/arch/arm/interrupts.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009, 2012-2013, 2016 ARM Limited
+ * Copyright (c) 2009, 2012-2013, 2016, 2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -58,7 +58,7 @@
SCR scr;
HCR hcr;
hcr = tc->readMiscReg(MISCREG_HCR);
- ExceptionLevel el = (ExceptionLevel) ((uint32_t) cpsr.el);
+ ExceptionLevel el = currEL(tc);
bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit,
hcr_mask_override_bit;
if (!highest_el_is_64)
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 2f7d916..73537a8 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -341,7 +341,7 @@
// EL0 controlled by PSTATE
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
- known = (cpsr.el == EL0);
+ known = (currEL(tc) == EL0);
aarch32 = (cpsr.width == 1);
} else {
known = true;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/20251
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc
Gerrit-Change-Number: 20251
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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