Hello kokoro, Alec Roelke,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/20308
to look at the new patch set (#2).
Change subject: arch-riscv: Fix load the trap vector(tvec) to PC
......................................................................
arch-riscv: Fix load the trap vector(tvec) to PC
This patch fixes how to load the BASE address in xvtec register
(x stand for m, s, u) when exception is triggerer. The xtvec only
stores the BASE[XLEN-1:2], so it needs to right-shift xtvec_BASE
by 2 then left-shift by 2 before setting it to PC.
Change-Id: I99c87f3270a9fa632585a2becc6f1fdb5e546448
---
M src/arch/riscv/faults.cc
1 file changed, 10 insertions(+), 1 deletion(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/20308
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I99c87f3270a9fa632585a2becc6f1fdb5e546448
Gerrit-Change-Number: 20308
Gerrit-PatchSet: 2
Gerrit-Owner: YIFEI LIU <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: newpatchset
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