[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix immediate decoding for integer shift immediate instru...

[Ian Jiang (Gerrit)]

Ian Jiang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/22803 )

Change subject: arch-riscv: Fix immediate decoding for integer shift  
immediate instructions
......................................................................

arch-riscv: Fix immediate decoding for integer shift immediate instructions

The "shamt" in integer shift immediate instructions is an unsigned
immediate encoded in bits[25:20]. While the original Gem5 uses bits[31:20]
as an int64_t. This patch fixes the problem by:
- Adding a new parameter "imm_code" for format IOp and use the correct
bitfields SHAMT5 or SHAMT6 to assign "imm_code" for each instruction.
- Use uint64_t instead of default int64_t to assign parameter "imm_type"
of format IOp.

Note: The original format IOp is renamed to format IFenceOp because the
synchronizing instructions fence and fence.i have to use the original
operation.

The instructions affected include:
- Shift Left Logical Immediate, slli
- Shift Right Logical Immediate, srli
- Shift Right Arithmetic Immediate, srai
- Shift Left Logical Word Immediate, slliw
- Shift Right Logical Word Immediate, srliw
- Shift Right Arithmetic Word Immediate, sraiw

Change-Id: Id1a39a13d217fa850217bceb765aad5c9599890c
Signed-off-by: Ian Jiang <ianjiang....@gmail.com>
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 21 insertions(+), 9 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 8fcfba6..e2faafb 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -400,7 +400,7 @@
         }

         0x03: decode FUNCT3 {
-            format IOp {
+            format IFenceOp {
                 0x0: fence({{
                 }}, uint64_t, IsMemBarrier, No_OpClass);
                 0x1: fence_i({{
@@ -415,10 +415,10 @@
                 }});
                 0x1: slli({{
                     Rd = Rs1 << SHAMT6;
-                }});
+                }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6; }});
                 0x2: slti({{
                     Rd = (Rs1_sd < imm) ? 1 : 0;
-                }});
+                }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6; }});
                 0x3: sltiu({{
                     Rd = (Rs1 < imm) ? 1 : 0;
                 }}, uint64_t);
@@ -428,10 +428,10 @@
                 0x5: decode SRTYPE {
                     0x0: srli({{
                         Rd = Rs1 >> SHAMT6;
-                    }});
+                    }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});
                     0x1: srai({{
                         Rd_sd = Rs1_sd >> SHAMT6;
-                    }});
+                    }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});
                 }
                 0x6: ori({{
                     Rd = Rs1 | imm;
@@ -453,14 +453,14 @@
                 }}, int32_t);
                 0x1: slliw({{
                     Rd_sd = Rs1_sw << SHAMT5;
-                }});
+                }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT5; }});
                 0x5: decode SRTYPE {
                     0x0: srliw({{
                         Rd_sd = (int32_t)(Rs1_uw >> SHAMT5);
-                    }});
+                    }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT5;  
}});
                     0x1: sraiw({{
                         Rd_sd = Rs1_sw >> SHAMT5;
-                    }});
+                    }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT5;  
}});
                 }
             }
         }
diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa
index 15d2681..9a1e941 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -298,7 +298,19 @@
     exec_output = BasicExecute.subst(iop)
 }};

-def format IOp(code, imm_type='int64_t', *opt_flags) {{
+def format IOp(code, imm_type='int64_t', imm_code='imm = sext<12>(IMM12);',
+              *opt_flags) {{
+    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+    iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
+        {'code': code, 'imm_code': imm_code,
+         'regs': ','.join(regs)}, opt_flags)
+    header_output = ImmDeclare.subst(iop)
+    decoder_output = ImmConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = ImmExecute.subst(iop)
+}};
+
+def format IFenceOp(code, imm_type='int64_t', *opt_flags) {{
     regs = ['_destRegIdx[0]','_srcRegIdx[0]']
     iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
         {'code': code, 'imm_code': 'imm = sext<12>(IMM12);',

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id1a39a13d217fa850217bceb765aad5c9599890c
Gerrit-Change-Number: 22803
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang <ianjiang....@gmail.com>
Gerrit-MessageType: newchange
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