Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23453 )
Change subject: riscv: Use a riscv specific GuestABI for riscv system calls.
......................................................................
riscv: Use a riscv specific GuestABI for riscv system calls.
Change-Id: Ia6ac34dfb38b71eff7b573b3c9ce477fef0ef5f7
---
M src/arch/riscv/linux/process.cc
M src/arch/riscv/linux/process.hh
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
4 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/src/arch/riscv/linux/process.cc
b/src/arch/riscv/linux/process.cc
index 8321301..730974b 100644
--- a/src/arch/riscv/linux/process.cc
+++ b/src/arch/riscv/linux/process.cc
@@ -120,7 +120,7 @@
return 0;
}
-std::map<int, SyscallDescABI<DefaultSyscallABI>>
+std::map<int, SyscallDescABI<RiscvProcess::SyscallABI>>
RiscvLinuxProcess64::syscallDescs = {
{0, { "io_setup" }},
{1, { "io_destroy" }},
@@ -452,7 +452,7 @@
{2011, { "getmainvars" }}
};
-std::map<int, SyscallDescABI<DefaultSyscallABI>>
+std::map<int, SyscallDescABI<RiscvProcess::SyscallABI>>
RiscvLinuxProcess32::syscallDescs = {
{0, { "io_setup" }},
{1, { "io_destroy" }},
diff --git a/src/arch/riscv/linux/process.hh
b/src/arch/riscv/linux/process.hh
index 7a2ad28..c6ae14e 100644
--- a/src/arch/riscv/linux/process.hh
+++ b/src/arch/riscv/linux/process.hh
@@ -59,7 +59,7 @@
void syscall(ThreadContext *tc, Fault *fault) override;
/// Array of syscall descriptors, indexed by call number.
- static std::map<int, SyscallDescABI<DefaultSyscallABI>> syscallDescs;
+ static std::map<int, SyscallDescABI<SyscallABI>> syscallDescs;
};
class RiscvLinuxProcess32 : public RiscvProcess32
@@ -79,7 +79,7 @@
void syscall(ThreadContext *tc, Fault *fault) override;
/// Array of syscall descriptors, indexed by call number.
- static std::map<int, SyscallDescABI<DefaultSyscallABI>> syscallDescs;
+ static std::map<int, SyscallDescABI<SyscallABI>> syscallDescs;
};
#endif // __RISCV_LINUX_PROCESS_HH__
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index ce49836..adc3982 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -270,3 +270,7 @@
tc->setIntReg(SyscallPseudoReturnReg, sysret.encodedValue());
}
}
+
+const std::vector<int> RiscvProcess::SyscallABI::ArgumentRegs = {
+ 10, 11, 12, 13, 14, 15, 16
+};
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index 71a0c7b..1782b52 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -39,6 +39,7 @@
#include "mem/page_table.hh"
#include "sim/process.hh"
+#include "sim/syscall_abi.hh"
class ObjectFile;
class System;
@@ -58,6 +59,36 @@
SyscallReturn return_value) override;
virtual bool mmapGrowsDown() const override { return false; }
+
+ //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
+ struct SyscallABI : public GenericSyscallABI64
+ {
+ static const std::vector<int> ArgumentRegs;
+ };
+};
+
+namespace GuestABI
+{
+
+template <>
+struct Result<RiscvProcess::SyscallABI, SyscallReturn>
+{
+ static void
+ store(ThreadContext *tc, const SyscallReturn &ret)
+ {
+ if (ret.suppressed() || ret.needsRetry())
+ return;
+
+ if (ret.successful()) {
+ // no error
+ tc->setIntReg(RiscvISA::ReturnValueReg, ret.returnValue());
+ } else {
+ // got an error, return details
+ tc->setIntReg(RiscvISA::ReturnValueReg, ret.encodedValue());
+ }
+ }
+};
+
};
class RiscvProcess64 : public RiscvProcess
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia6ac34dfb38b71eff7b573b3c9ce477fef0ef5f7
Gerrit-Change-Number: 23453
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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