[gem5-dev] Change in gem5/gem5[master]: sparc: Introduce a BitUnion for the CCR register.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23446 )

Change subject: sparc: Introduce a BitUnion for the CCR register.
......................................................................

sparc: Introduce a BitUnion for the CCR register.

This avoids opaque masks when accessing fields of this register.

Change-Id: If20d82c7c6401e6b1b35bb6d2c69542a56e2fb45
---
M src/arch/sparc/faults.cc
M src/arch/sparc/miscregs.hh
M src/arch/sparc/process.cc
3 files changed, 30 insertions(+), 17 deletions(-)



diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 0057f12..ca63a04 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -306,7 +306,7 @@
     RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
-    RegVal CCR = tc->readIntReg(INTREG_CCR);
+    CCR ccr = tc->readIntReg(INTREG_CCR);
     RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
     RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
     RegVal CANSAVE = tc->readMiscRegNoEffect(INTREG_CANSAVE);
@@ -320,7 +320,7 @@
     // set TSTATE.gl to gl
     replaceBits(TSTATE, 42, 40, GL);
     // set TSTATE.ccr to ccr
-    replaceBits(TSTATE, 39, 32, CCR);
+    replaceBits(TSTATE, 39, 32, ccr);
     // set TSTATE.asi to asi
     replaceBits(TSTATE, 31, 24, ASI);
     // set TSTATE.pstate to pstate
@@ -385,7 +385,7 @@
     RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
     HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
-    RegVal CCR = tc->readIntReg(INTREG_CCR);
+    CCR ccr = tc->readIntReg(INTREG_CCR);
     RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
     RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
     RegVal CANSAVE = tc->readIntReg(INTREG_CANSAVE);
@@ -403,7 +403,7 @@
     // set TSTATE.gl to gl
     replaceBits(TSTATE, 42, 40, GL);
     // set TSTATE.ccr to ccr
-    replaceBits(TSTATE, 39, 32, CCR);
+    replaceBits(TSTATE, 39, 32, ccr);
     // set TSTATE.asi to asi
     replaceBits(TSTATE, 31, 24, ASI);
     // set TSTATE.pstate to pstate
diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh
index 6c5118f..2f98876 100644
--- a/src/arch/sparc/miscregs.hh
+++ b/src/arch/sparc/miscregs.hh
@@ -136,6 +136,21 @@
     Bitfield<11> pid1;
 EndBitUnion(PSTATE)

+BitUnion8(CCR)
+    SubBitUnion(xcc, 7, 4)
+        Bitfield<7> n;
+        Bitfield<6> z;
+        Bitfield<5> v;
+        Bitfield<4> c;
+    EndSubBitUnion(xcc)
+    SubBitUnion(icc, 3, 0)
+        Bitfield<3> n;
+        Bitfield<2> z;
+        Bitfield<1> v;
+        Bitfield<0> c;
+    EndSubBitUnion(icc)
+EndBitUnion(CCR)
+
 struct STS
 {
     const static int st_idle     = 0x00;
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index dd9215f..d064de2 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -512,23 +512,21 @@
 {
     // check for error condition.  SPARC syscall convention is to
     // indicate success/failure in reg the carry bit of the ccr
-    // and put the return value itself in the standard return value reg ().
+    // and put the return value itself in the standard return value reg.
     PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    CCR ccr = tc->readIntReg(INTREG_CCR);
+    RegVal val;
     if (sysret.successful()) {
-        // no error, clear XCC.C
-        tc->setIntReg(INTREG_CCR, tc->readIntReg(INTREG_CCR) & 0xEE);
-        RegVal val = sysret.returnValue();
-        if (pstate.am)
-            val = bits(val, 31, 0);
-        tc->setIntReg(ReturnValueReg, val);
+        ccr.xcc.c = ccr.icc.c = 0;
+        val = sysret.returnValue();
     } else {
-        // got an error, set XCC.C
-        tc->setIntReg(INTREG_CCR, tc->readIntReg(INTREG_CCR) | 0x11);
-        RegVal val = sysret.errnoValue();
-        if (pstate.am)
-            val = bits(val, 31, 0);
-        tc->setIntReg(ReturnValueReg, val);
+        ccr.xcc.c = ccr.icc.c = 1;
+        val = sysret.errnoValue();
     }
+    tc->setIntReg(INTREG_CCR, ccr);
+    if (pstate.am)
+        val = bits(val, 31, 0);
+    tc->setIntReg(ReturnValueReg, val);
     if (sysret.count() > 1)
         tc->setIntReg(SyscallPseudoReturnReg, sysret.value2());
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If20d82c7c6401e6b1b35bb6d2c69542a56e2fb45
Gerrit-Change-Number: 23446
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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