Hi. Please take a look at this when you have a chance and ask questions/provide feedback. This is primarily focused on fast model, but there are implications for pseudo instruction support in ARM in general.
Gabe On Wed, Jan 15, 2020 at 7:28 PM Gabe Black <[email protected]> wrote: > Hi folks. The existing mechanisms for supporting pseudo instructions in > the fast model based CPUs won't work, and so a new mechanism is needed. > Also, because there are already a few different ways to call pseudo > instructions, it would be nice to consolidate or at least coordinate them, > and to avoid having to build magic, system specific addresses into the m5 > utility binary. Here is a design doc I wrote about that: > > > https://docs.google.com/document/d/1I7Jaj5_HssMSlvf-QKL1IsuBvV0Bm6a64At5vjhMIhU/edit?usp=sharing > > This is focused on fast models, but also proposes a way to rework/expand > how pseudo instructions are called in general and the m5 utility so that > they're a little easier to use across the board. > > Gabe > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
