Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25145 )

Change subject: sim: Move guts of quiesce and quisceTick from ThreadContext to System.
......................................................................

sim: Move guts of quiesce and quisceTick from ThreadContext to System.

The functions in ThreadContext are now just convenience wrappers.

Change-Id: Ib56c4bdd27e611fb667a8056dfae37065f4034eb
---
M src/cpu/thread_context.cc
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 90 insertions(+), 37 deletions(-)



diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index bebfe91..f3c8c4f 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -132,28 +132,14 @@
 void
 ThreadContext::quiesce()
 {
-    DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name());
-
-    suspend();
-    if (getKernelStats())
-        getKernelStats()->quiesce();
+    getSystemPtr()->threads.quiesce(contextId());
 }


 void
 ThreadContext::quiesceTick(Tick resume)
 {
-    BaseCPU *cpu = getCpuPtr();
-
-    EndQuiesceEvent *quiesceEvent = getQuiesceEvent();
-
-    cpu->reschedule(quiesceEvent, resume, true);
-
-    DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
-
-    suspend();
-    if (getKernelStats())
-        getKernelStats()->quiesce();
+    getSystemPtr()->threads.quiesceTick(contextId(), resume);
 }

 void
@@ -250,26 +236,8 @@
     ntc.setContextId(otc.contextId());
     ntc.setThreadId(otc.threadId());

-    if (FullSystem) {
+    if (FullSystem)
         assert(ntc.getSystemPtr() == otc.getSystemPtr());

-        BaseCPU *ncpu(ntc.getCpuPtr());
-        assert(ncpu);
-        EndQuiesceEvent *oqe(otc.getQuiesceEvent());
-        assert(oqe);
-        assert(oqe->tc == &otc);
-
-        BaseCPU *ocpu(otc.getCpuPtr());
-        assert(ocpu);
-        EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
-        assert(nqe);
-        assert(nqe->tc == &ntc);
-
-        if (oqe->scheduled()) {
-            ncpu->schedule(nqe, oqe->when());
-            ocpu->deschedule(oqe);
-        }
-    }
-
     otc.setStatus(ThreadContext::Halted);
 }
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 547bdd5..a7c0a9f 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -87,6 +87,31 @@

 vector<System *> System::systemList;

+void
+System::Threads::Thread::resume()
+{
+#   if THE_ISA != NULL_ISA
+    DPRINTFS(Quiesce, context->getCpuPtr(), "activating\n");
+    context->activate();
+#   endif
+}
+
+std::string
+System::Threads::Thread::name() const
+{
+    assert(context);
+    return csprintf("%s.threads[%d]", context->getSystemPtr()->name(),
+            context->contextId());
+}
+
+void
+System::Threads::Thread::quiesce() const
+{
+    context->suspend();
+    if (context->getKernelStats())
+        context->getKernelStats()->quiesce();
+}
+
 ContextID
 System::Threads::insert(ThreadContext *tc, ContextID id)
 {
@@ -105,6 +130,7 @@

     auto &t = thread(id);
     t.context = tc;
+    t.resumeEvent = new EventWrapper<Thread, &Thread::resume>(t);
 #   if THE_ISA != NULL_ISA
     int port = getRemoteGDBPort();
     if (port) {
@@ -120,9 +146,17 @@
 System::Threads::replace(ThreadContext *tc, ContextID id)
 {
     auto &t = thread(id);
-    t.context = tc;
+    panic_if(!t.context, "Can't replace a context which doesn't exist.");
     if (t.gdb)
         t.gdb->replaceThreadContext(tc);
+#   if THE_ISA != NULL_ISA
+    if (t.resumeEvent->scheduled()) {
+        Tick when = t.resumeEvent->when();
+        t.context->getCpuPtr()->deschedule(t.resumeEvent);
+        tc->getCpuPtr()->schedule(t.resumeEvent, when);
+    }
+#   endif
+    t.context = tc;
 }

 ThreadContext *
@@ -149,6 +183,31 @@
     return count;
 }

+void
+System::Threads::quiesce(ContextID id)
+{
+    auto &t = thread(id);
+#   if THE_ISA != NULL_ISA
+    BaseCPU *cpu = t.context->getCpuPtr();
+    DPRINTFS(Quiesce, cpu, "quiesce()\n");
+#   endif
+    t.quiesce();
+}
+
+void
+System::Threads::quiesceTick(ContextID id, Tick when)
+{
+#   if THE_ISA != NULL_ISA
+    auto &t = thread(id);
+    BaseCPU *cpu = t.context->getCpuPtr();
+
+    DPRINTFS(Quiesce, cpu, "quiesceTick until %u\n", when);
+    t.quiesce();
+
+    cpu->reschedule(t.resumeEvent, when, true);
+#   endif
+}
+
 int System::numSystemsRunning = 0;

 System::System(Params *p)
@@ -372,6 +431,14 @@
 {
     SERIALIZE_SCALAR(pagePtr);

+    for (auto &t: threads.threads) {
+        Tick when = 0;
+        if (t.resumeEvent && t.resumeEvent->scheduled())
+            when = t.resumeEvent->when();
+        ContextID id = t.context->contextId();
+        paramOut(cp, csprintf("quiesceEndTick_%d", id), when);
+    }
+
     // also serialize the memories in the system
     physmem.serializeSection(cp, "physmem");
 }
@@ -382,6 +449,18 @@
 {
     UNSERIALIZE_SCALAR(pagePtr);

+    for (auto &t: threads.threads) {
+        Tick when;
+        ContextID id = t.context->contextId();
+        if (!optParamIn(cp, csprintf("quiesceEndTick_%d", id), when) ||
+                !when || !t.resumeEvent) {
+            continue;
+        }
+#       if THE_ISA != NULL_ISA
+        t.context->getCpuPtr()->schedule(t.resumeEvent, when);
+#       endif
+    }
+
     // also unserialize the memories in the system
     physmem.unserializeSection(cp, "physmem");
 }
diff --git a/src/sim/system.hh b/src/sim/system.hh
index ce01750..8145e8d 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -113,6 +113,11 @@
             ThreadContext *context = nullptr;
             bool active = false;
             BaseRemoteGDB *gdb = nullptr;
+            Event *resumeEvent = nullptr;
+
+            void resume();
+            std::string name() const;
+            void quiesce() const;
         };

         std::vector<Thread> threads;
@@ -212,7 +217,8 @@
             return count;
         }

-        void resume(ContextID id, Tick when);
+        void quiesce(ContextID id);
+        void quiesceTick(ContextID id, Tick when);

         const_iterator begin() const { return const_iterator(*this, 0); }
const_iterator end() const { return const_iterator(*this, size()); }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25145
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib56c4bdd27e611fb667a8056dfae37065f4034eb
Gerrit-Change-Number: 25145
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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