Hello, Question about the L3 cache's role in the MOESI_AMD_Base protocol (and by extension GPU_VIPER which seems to extend it).
There seems to be an l3 cache in the directory controller, but it looks like the ports that go to the L3 Cache are never activated (I added some dprintfs in the .sm files). The L3Cache has a bunch of wireBuffers, and there are functions in the MOESI_AMD_BASE.py and GPU_VIPER.py files to connect those wirebuffers, but they are never called.. I'm investigating, but I figured I'd ask and see if anyone has information about this. Is the L3 not a functioning feature? Cheers, Dan Gerzhoy _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
