Nils Asmussen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25645 )
Change subject: arch-riscv: added support for pseudo instructions.
......................................................................
arch-riscv: added support for pseudo instructions.
Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/pseudo.cc
A src/arch/riscv/insts/pseudo.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/formats.isa
A src/arch/riscv/isa/formats/m5ops.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/operands.isa
8 files changed, 445 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index d9e47c3..8e292f1 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,5 +1,6 @@
# Copyright (c) 2015 RISC-V Foundation
# Copyright (c) 2017 The University of Virginia
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -31,5 +32,6 @@
Source('amo.cc')
Source('compressed.cc')
Source('mem.cc')
+ Source('pseudo.cc')
Source('standard.cc')
Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/pseudo.cc b/src/arch/riscv/insts/pseudo.cc
new file mode 100644
index 0000000..e0a1b4d
--- /dev/null
+++ b/src/arch/riscv/insts/pseudo.cc
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/riscv/insts/pseudo.hh"
+
+#include <sstream>
+#include <string>
+
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+PseudoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ return mnemonic;
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh
new file mode 100644
index 0000000..3c19d87
--- /dev/null
+++ b/src/arch/riscv/insts/pseudo.hh
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Barkhausen Institut
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_INSTS_PSEUDO_HH__
+#define __ARCH_RISCV_INSTS_PSEUDO_HH__
+
+#include <string>
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class PseudoOp : public RiscvStaticInst
+{
+ protected:
+ using RiscvStaticInst::RiscvStaticInst;
+
+ std::string generateDisassembly(
+ Addr pc, const SymbolTable *symtab) const override;
+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_PSEUDO_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 63cf1e4..65e8409 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -1832,5 +1833,7 @@
}}, IsNonSpeculative, No_OpClass);
}
}
+
+ 0x1e: M5ops::m5ops();
}
}
diff --git a/src/arch/riscv/isa/formats/formats.isa
b/src/arch/riscv/isa/formats/formats.isa
index 0f7dc42..2a6b910 100644
--- a/src/arch/riscv/isa/formats/formats.isa
+++ b/src/arch/riscv/isa/formats/formats.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -39,5 +40,8 @@
// Include formats for nonstandard extensions
##include "compressed.isa"
+// Pseudo operations
+##include "m5ops.isa"
+
// Include the unknown
##include "unknown.isa"
diff --git a/src/arch/riscv/isa/formats/m5ops.isa
b/src/arch/riscv/isa/formats/m5ops.isa
new file mode 100644
index 0000000..8726961
--- /dev/null
+++ b/src/arch/riscv/isa/formats/m5ops.isa
@@ -0,0 +1,328 @@
+//
+// Copyright (c) 2010, 2012-2013 ARM Limited
+// Copyright (c) 2020 Barkhausen Institut
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+let {{
+ armCode = '''
+ PseudoInst::arm(xc->tcBase());
+ '''
+
+ armIop = InstObjParams("arm", "Arm", "PseudoOp",
+ { "code": armCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(armIop)
+ decoder_output += BasicConstructor.subst(armIop)
+ exec_output += BasicExecute.subst(armIop)
+
+ quiesceCode = '''
+ PseudoInst::quiesce(xc->tcBase());
+ '''
+
+ quiesceIop = InstObjParams("quiesce", "Quiesce", "PseudoOp",
+ { "code": quiesceCode },
+ ["IsNonSpeculative", "IsQuiesce"])
+ header_output += BasicDeclare.subst(quiesceIop)
+ decoder_output += BasicConstructor.subst(quiesceIop)
+ exec_output += BasicExecute.subst(quiesceIop)
+
+ quiesceNsCode = '''
+ PseudoInst::quiesceNs(xc->tcBase(), a0);
+ '''
+
+ quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PseudoOp",
+ { "code": quiesceNsCode },
+ ["IsNonSpeculative", "IsQuiesce"])
+ header_output += BasicDeclare.subst(quiesceNsIop)
+ decoder_output += BasicConstructor.subst(quiesceNsIop)
+ exec_output += BasicExecute.subst(quiesceNsIop)
+
+ quiesceCyclesCode = '''
+ PseudoInst::quiesceCycles(xc->tcBase(), a0);
+ '''
+
+ quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles",
+ "PseudoOp",
+ { "code": quiesceCyclesCode },
+ ["IsNonSpeculative", "IsQuiesce",
+ "IsUnverifiable"])
+ header_output += BasicDeclare.subst(quiesceCyclesIop)
+ decoder_output += BasicConstructor.subst(quiesceCyclesIop)
+ exec_output += BasicExecute.subst(quiesceCyclesIop)
+
+ quiesceTimeCode = '''
+ a0 = PseudoInst::quiesceTime(xc->tcBase());
+ '''
+
+ quiesceTimeIop =
InstObjParams("quiesceTime", "QuiesceTime", "PseudoOp",
+ { "code": quiesceTimeCode },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(quiesceTimeIop)
+ decoder_output += BasicConstructor.subst(quiesceTimeIop)
+ exec_output += BasicExecute.subst(quiesceTimeIop)
+
+ rpnsCode = '''
+ a0 = PseudoInst::rpns(xc->tcBase());
+ '''
+
+ rpnsIop = InstObjParams("rpns", "Rpns", "PseudoOp",
+ { "code": rpnsCode },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(rpnsIop)
+ decoder_output += BasicConstructor.subst(rpnsIop)
+ exec_output += BasicExecute.subst(rpnsIop)
+
+ wakeCpuCode = '''
+ PseudoInst::wakeCPU(xc->tcBase(), a0);
+ '''
+
+ wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PseudoOp",
+ { "code": wakeCpuCode },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(wakeCPUIop)
+ decoder_output += BasicConstructor.subst(wakeCPUIop)
+ exec_output += BasicExecute.subst(wakeCPUIop)
+
+ m5fail_code = '''
+ PseudoInst::m5fail(xc->tcBase(), a0, a1);
+ '''
+
+ m5failIop = InstObjParams("m5fail", "M5fail", "PseudoOp",
+ { "code": m5fail_code },
+ ["No_OpClass", "IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5failIop)
+ decoder_output += BasicConstructor.subst(m5failIop)
+ exec_output += BasicExecute.subst(m5failIop)
+
+ m5exit_code = '''
+ PseudoInst::m5exit(xc->tcBase(), a0);
+ '''
+
+ m5exitIop = InstObjParams("m5exit", "M5exit", "PseudoOp",
+ { "code": m5exit_code },
+ ["No_OpClass", "IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5exitIop)
+ decoder_output += BasicConstructor.subst(m5exitIop)
+ exec_output += BasicExecute.subst(m5exitIop)
+
+ loadsymbolCode = '''
+ PseudoInst::loadsymbol(xc->tcBase());
+ '''
+
+ loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PseudoOp",
+ { "code": loadsymbolCode },
+ ["No_OpClass", "IsNonSpeculative"])
+ header_output += BasicDeclare.subst(loadsymbolIop)
+ decoder_output += BasicConstructor.subst(loadsymbolIop)
+ exec_output += BasicExecute.subst(loadsymbolIop)
+
+ initparamCode = '''
+ a0 = PseudoInst::initParam(xc->tcBase(), a0, a1);
+ '''
+
+ initparamIop = InstObjParams("initparam", "Initparam", "PseudoOp",
+ { "code": initparamCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(initparamIop)
+ decoder_output += BasicConstructor.subst(initparamIop)
+ exec_output += BasicExecute.subst(initparamIop)
+
+ resetstats_code = '''
+ PseudoInst::resetstats(xc->tcBase(), a0, a1);
+ '''
+
+ resetstatsIop = InstObjParams("resetstats", "Resetstats", "PseudoOp",
+ { "code": resetstats_code },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(resetstatsIop)
+ decoder_output += BasicConstructor.subst(resetstatsIop)
+ exec_output += BasicExecute.subst(resetstatsIop)
+
+ dumpstats_code = '''
+ PseudoInst::dumpstats(xc->tcBase(), a0, a1);
+ '''
+
+ dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PseudoOp",
+ { "code": dumpstats_code },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(dumpstatsIop)
+ decoder_output += BasicConstructor.subst(dumpstatsIop)
+ exec_output += BasicExecute.subst(dumpstatsIop)
+
+ dumpresetstats_code = '''
+ PseudoInst::dumpresetstats(xc->tcBase(), a0, a1);
+ '''
+
+ dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats",
+ "PseudoOp",
+ { "code": dumpresetstats_code },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(dumpresetstatsIop)
+ decoder_output += BasicConstructor.subst(dumpresetstatsIop)
+ exec_output += BasicExecute.subst(dumpresetstatsIop)
+
+ m5checkpoint_code = '''
+ PseudoInst::m5checkpoint(xc->tcBase(), a0, a1);
+ '''
+
+ m5checkpointIop =
InstObjParams("m5checkpoint", "M5checkpoint", "PseudoOp",
+ { "code": m5checkpoint_code },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(m5checkpointIop)
+ decoder_output += BasicConstructor.subst(m5checkpointIop)
+ exec_output += BasicExecute.subst(m5checkpointIop)
+
+ m5readfileCode = '''
+ a0 = PseudoInst::readfile(xc->tcBase(), a0, a1, a2);
+ '''
+
+ m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PseudoOp",
+ { "code": m5readfileCode },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(m5readfileIop)
+ decoder_output += BasicConstructor.subst(m5readfileIop)
+ exec_output += BasicExecute.subst(m5readfileIop)
+
+ m5writefileCode = '''
+ a0 = PseudoInst::writefile(xc->tcBase(), a0, a1, a2, a3);
+ '''
+
+ m5writefileIop =
InstObjParams("m5writefile", "M5writefile", "PseudoOp",
+ { "code": m5writefileCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5writefileIop)
+ decoder_output += BasicConstructor.subst(m5writefileIop)
+ exec_output += BasicExecute.subst(m5writefileIop)
+
+ m5breakCode = '''
+ PseudoInst::debugbreak(xc->tcBase());
+ '''
+
+ m5breakIop = InstObjParams("m5break", "M5break", "PseudoOp",
+ { "code": m5breakCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5breakIop)
+ decoder_output += BasicConstructor.subst(m5breakIop)
+ exec_output += BasicExecute.subst(m5breakIop)
+
+ m5switchcpuCode = '''
+ PseudoInst::switchcpu(xc->tcBase());
+ '''
+
+ m5switchcpuIop =
InstObjParams("m5switchcpu", "M5switchcpu", "PseudoOp",
+ { "code": m5switchcpuCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5switchcpuIop)
+ decoder_output += BasicConstructor.subst(m5switchcpuIop)
+ exec_output += BasicExecute.subst(m5switchcpuIop)
+
+ m5addsymbolCode = '''
+ PseudoInst::addsymbol(xc->tcBase(), a0, a1);
+ '''
+
+ m5addsymbolIop =
InstObjParams("m5addsymbol", "M5addsymbol", "PseudoOp",
+ { "code": m5addsymbolCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5addsymbolIop)
+ decoder_output += BasicConstructor.subst(m5addsymbolIop)
+ exec_output += BasicExecute.subst(m5addsymbolIop)
+
+ m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
+ xc->pcState().pc());'''
+
+ m5panicIop = InstObjParams("m5panic", "M5panic", "PseudoOp",
+ { "code": m5panicCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5panicIop)
+ decoder_output += BasicConstructor.subst(m5panicIop)
+ exec_output += BasicExecute.subst(m5panicIop)
+
+ m5workbeginCode = '''
+ PseudoInst::workbegin(xc->tcBase(), a0, a1);
+ '''
+
+ m5workbeginIop =
InstObjParams("m5workbegin", "M5workbegin", "PseudoOp",
+ { "code": m5workbeginCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5workbeginIop)
+ decoder_output += BasicConstructor.subst(m5workbeginIop)
+ exec_output += BasicExecute.subst(m5workbeginIop)
+
+ m5workendCode = '''
+ PseudoInst::workend(xc->tcBase(), a0, a1);
+ '''
+
+ m5workendIop = InstObjParams("m5workend", "M5workend", "PseudoOp",
+ { "code": m5workendCode },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5workendIop)
+ decoder_output += BasicConstructor.subst(m5workendIop)
+ exec_output += BasicExecute.subst(m5workendIop)
+}};
+
+def format M5ops() {{
+ decode_block = '''
+ {
+ const uint32_t m5func = bits(machInst, 31, 25);
+ switch(m5func) {
+ case M5OP_ARM: return new Arm(machInst);
+ case M5OP_QUIESCE: return new Quiesce(machInst);
+ case M5OP_QUIESCE_NS: return new QuiesceNs(machInst);
+ case M5OP_QUIESCE_CYCLE: return new QuiesceCycles(machInst);
+ case M5OP_QUIESCE_TIME: return new QuiesceTime(machInst);
+ case M5OP_RPNS: return new Rpns(machInst);
+ case M5OP_WAKE_CPU: return new WakeCPU(machInst);
+ case M5OP_EXIT: return new M5exit(machInst);
+ case M5OP_FAIL: return new M5fail(machInst);
+ case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
+ case M5OP_INIT_PARAM: return new Initparam(machInst);
+ case M5OP_RESET_STATS: return new Resetstats(machInst);
+ case M5OP_DUMP_STATS: return new Dumpstats(machInst);
+ case M5OP_DUMP_RESET_STATS: return new
Dumpresetstats(machInst);
+ case M5OP_CHECKPOINT: return new M5checkpoint(machInst);
+ case M5OP_WRITE_FILE: return new M5writefile(machInst);
+ case M5OP_READ_FILE: return new M5readfile(machInst);
+ case M5OP_DEBUG_BREAK: return new M5break(machInst);
+ case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
+ case M5OP_ADD_SYMBOL: return new M5addsymbol(machInst);
+ case M5OP_PANIC: return new M5panic(machInst);
+ case M5OP_WORK_BEGIN: return new M5workbegin(machInst);
+ case M5OP_WORK_END: return new M5workend(machInst);
+ default: return new Unknown(machInst);
+ }
+ }
+ '''
+}};
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 2d355ba..9db8c9e 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -42,6 +43,7 @@
#include "arch/riscv/insts/amo.hh"
#include "arch/riscv/insts/compressed.hh"
#include "arch/riscv/insts/mem.hh"
+#include "arch/riscv/insts/pseudo.hh"
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "arch/riscv/insts/unknown.hh"
@@ -57,6 +59,8 @@
#include <limits>
#include <string>
+#include <gem5/asm/generic/m5ops.h>
+
#include "arch/riscv/decoder.hh"
#include "arch/riscv/faults.hh"
#include "arch/riscv/tlb.hh"
@@ -90,6 +94,7 @@
#include "mem/request.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
+#include "sim/pseudo_inst.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
diff --git a/src/arch/riscv/isa/operands.isa
b/src/arch/riscv/isa/operands.isa
index 7c80b8a..41e0a4b 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -53,6 +54,11 @@
'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1),
'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2),
+ 'a0': ('IntReg', 'ud', '10', 'IsInteger', 1),
+ 'a1': ('IntReg', 'ud', '11', 'IsInteger', 2),
+ 'a2': ('IntReg', 'ud', '12', 'IsInteger', 3),
+ 'a3': ('IntReg', 'ud', '13', 'IsInteger', 4),
+
'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
Gerrit-Change-Number: 25645
Gerrit-PatchSet: 1
Gerrit-Owner: Nils Asmussen <nils.asmus...@barkhauseninstitut.org>
Gerrit-MessageType: newchange
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