Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26324 )
Change subject: tests: Migrated 10.linux-boot scons-based test to testlib
......................................................................
tests: Migrated 10.linux-boot scons-based test to testlib
This test has purposely been designed to be easily extendible for future
boot tests. Right now, it only runs a basic linux boot tests.
Change-Id: I81385b5dfc0764af2ec02999eb26e523bd09a595
Issue-on: https://gem5.atlassian.net/browse/GEM5-109
---
A tests/gem5/boot-tests/run_exit.py
A tests/gem5/boot-tests/system/MI_example_caches.py
A tests/gem5/boot-tests/system/__init__.py
A tests/gem5/boot-tests/system/caches.py
A tests/gem5/boot-tests/system/fs_tools.py
A tests/gem5/boot-tests/system/ruby_system.py
A tests/gem5/boot-tests/system/system.py
A tests/gem5/boot-tests/test_linux_boot.py
8 files changed, 1,259 insertions(+), 0 deletions(-)
diff --git a/tests/gem5/boot-tests/run_exit.py
b/tests/gem5/boot-tests/run_exit.py
new file mode 100644
index 0000000..377eaf9
--- /dev/null
+++ b/tests/gem5/boot-tests/run_exit.py
@@ -0,0 +1,102 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+"""
+"""
+
+import sys
+import os
+
+import m5
+import m5.ticks
+from m5.objects import *
+
+# For the next line...
+sys.path.append(os.path.dirname(__file__) + '/../../../configs/common/')
+import SimpleOpts
+
+from system import *
+
+SimpleOpts.set_usage(
+ "usage: %prog [options] kernel disk cpu_type mem_sys num_cpus
boot_type")
+
+SimpleOpts.add_option("--allow_listeners", default=False,
action="store_true",
+ help="Listeners disabled by default")
+
+if __name__ == "__m5_main__":
+ (opts, args) = SimpleOpts.parse_args()
+
+ if len(args) != 6:
+ SimpleOpts.print_help()
+ m5.fatal("Bad arguments")
+
+ kernel, disk, cpu_type, mem_sys, num_cpus, boot_type = args
+ num_cpus = int(num_cpus)
+
+ # create the system we are going to simulate
+ if mem_sys == "classic":
+ system = MySystem(kernel, disk, cpu_type, num_cpus, opts)
+ elif mem_sys == "ruby":
+ system = MyRubySystem(kernel, disk, cpu_type, num_cpus, opts)
+ else:
+ m5.fatal("Bad option for mem_sys, should be 'ruby' or 'classic'")
+
+ if boot_type == "init":
+ # Simply run "exit.sh"
+ system.boot_osflags += ' init=/root/exit.sh'
+ else:
+ if boot_type != "systemd":
+ SimpleOpts.print_help()
+ m5.fatal("Bad option for boot_type. init or systemd.")
+
+ # set up the root SimObject and start the simulation
+ root = Root(full_system = True, system = system)
+
+ if system.getHostParallel():
+ # Required for running kvm on multiple host cores.
+ # Uses gem5's parallel event queue feature
+ # Note: The simulator is quite picky about this number!
+ root.sim_quantum = int(1e9) # 1 ms
+
+ # Required for long-running jobs
+ if not opts.allow_listeners:
+ m5.disableAllListeners()
+
+ # instantiate all of the objects we've created above
+ m5.instantiate()
+
+ print("Running the simulation")
+ exit_event = m5.simulate()
+
+ if exit_event.getCause() != "m5_exit instruction encountered":
+ print("Failed to exit correctly")
+ exit(1)
+ else:
+ print("Success!")
+ exit(0)
diff --git a/tests/gem5/boot-tests/system/MI_example_caches.py
b/tests/gem5/boot-tests/system/MI_example_caches.py
new file mode 100644
index 0000000..30ccf4a
--- /dev/null
+++ b/tests/gem5/boot-tests/system/MI_example_caches.py
@@ -0,0 +1,278 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a set of Ruby caches, the Ruby network, and a simple
+point-to-point topology.
+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+You can change simple_ruby to import from this file instead of from
msi_caches
+to use the MI_example protocol instead of MSI.
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+ also needs to be updated. For now, email Jason
<ja...@lowepower.com>
+
+"""
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+import math
+
+from m5.defines import buildEnv
+from m5.util import fatal, panic
+
+from m5.objects import *
+
+class MyCacheSystem(RubySystem):
+
+ def __init__(self):
+ if buildEnv['PROTOCOL'] != 'MI_example':
+ fatal("This system assumes MI_example!")
+
+ super(MyCacheSystem, self).__init__()
+
+ def setup(self, system, cpus, mem_ctrls, dma_ports, iobus):
+ """Set up the Ruby cache subsystem. Note: This can't be done in the
+ constructor because many of these items require a pointer to the
+ ruby system (self). This causes infinite recursion in
initialize()
+ if we do this in the __init__.
+ """
+ # Ruby's global network.
+ self.network = MyNetwork(self)
+
+ # MI example uses 5 virtual networks
+ self.number_of_virtual_networks = 5
+ self.network.number_of_virtual_networks = 5
+
+ # There is a single global list of all of the controllers to make
it
+ # easier to connect everything to the global network. This can be
+ # customized depending on the topology/network requirements.
+ # Create one controller for each L1 cache (and the cache mem obj.)
+ # Create a single directory controller (Really the memory cntrl)
+ self.controllers = \
+ [L1Cache(system, self, cpu) for cpu in cpus] + \
+ [DirController(self, system.mem_ranges, mem_ctrls)] + \
+ [DMAController(self) for i in range(len(dma_ports))]
+
+ # Create one sequencer per CPU. In many systems this is more
+ # complicated since you have to create sequencers for DMA
controllers
+ # and other controllers, too.
+ self.sequencers = [RubySequencer(version = i,
+ # I/D cache is combined and grab from ctrl
+ icache = self.controllers[i].cacheMemory,
+ dcache = self.controllers[i].cacheMemory,
+ clk_domain =
self.controllers[i].clk_domain,
+ pio_master_port = iobus.slave,
+ mem_master_port = iobus.slave,
+ pio_slave_port = iobus.master
+ ) for i in range(len(cpus))] + \
+ [DMASequencer(version = i,
+ slave = port)
+ for i,port in enumerate(dma_ports)
+ ]
+
+ for i,c in enumerate(self.controllers[0:len(cpus)]):
+ c.sequencer = self.sequencers[i]
+
+ for i,d in enumerate(self.controllers[-len(dma_ports):]):
+ i += len(cpus)
+ d.dma_sequencer = self.sequencers[i]
+
+ self.num_of_sequencers = len(self.sequencers)
+
+ # Create the network and connect the controllers.
+ # NOTE: This is quite different if using Garnet!
+ self.network.connectControllers(self.controllers)
+ self.network.setup_buffers()
+
+ # Set up a proxy port for the system_port. Used for load binaries
and
+ # other functional-only things.
+ self.sys_port_proxy = RubyPortProxy()
+ system.system_port = self.sys_port_proxy.slave
+ self.sys_port_proxy.pio_master_port = iobus.slave
+
+ # Connect the cpu's cache, interrupt, and TLB ports to Ruby
+ for i,cpu in enumerate(cpus):
+ cpu.icache_port = self.sequencers[i].slave
+ cpu.dcache_port = self.sequencers[i].slave
+ isa = buildEnv['TARGET_ISA']
+ if isa == 'x86':
+ cpu.interrupts[0].pio = self.sequencers[i].master
+ cpu.interrupts[0].int_master = self.sequencers[i].slave
+ cpu.interrupts[0].int_slave = self.sequencers[i].master
+ if isa == 'x86' or isa == 'arm':
+ cpu.itb.walker.port = self.sequencers[i].slave
+ cpu.dtb.walker.port = self.sequencers[i].slave
+
+
+class L1Cache(L1Cache_Controller):
+
+ _version = 0
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
+ def __init__(self, system, ruby_system, cpu):
+ """CPUs are needed to grab the clock domain and system is needed
for
+ the cache block size.
+ """
+ super(L1Cache, self).__init__()
+
+ self.version = self.versionCount()
+ # This is the cache memory object that stores the cache data and
tags
+ self.cacheMemory = RubyCache(size = '16kB',
+ assoc = 8,
+ start_index_bit =
self.getBlockSizeBits(system))
+ self.clk_domain = cpu.clk_domain
+ self.send_evictions = self.sendEvicts(cpu)
+ self.ruby_system = ruby_system
+ self.connectQueues(ruby_system)
+
+ def getBlockSizeBits(self, system):
+ bits = int(math.log(system.cache_line_size, 2))
+ if 2**bits != system.cache_line_size.value:
+ panic("Cache line size not a power of 2!")
+ return bits
+
+ def sendEvicts(self, cpu):
+ """True if the CPU model or ISA requires sending evictions from
caches
+ to the CPU. Two scenarios warrant forwarding evictions to the
CPU:
+ 1. The O3 model must keep the LSQ coherent with the caches
+ 2. The x86 mwait instruction is built on top of coherence
+ 3. The local exclusive monitor in ARM systems
+ """
+ if type(cpu) is DerivO3CPU or \
+ buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+ return True
+ return False
+
+ def connectQueues(self, ruby_system):
+ """Connect all of the queues for this controller.
+ """
+ self.mandatoryQueue = MessageBuffer()
+ self.requestFromCache = MessageBuffer(ordered = True)
+ self.requestFromCache.master = ruby_system.network.slave
+ self.responseFromCache = MessageBuffer(ordered = True)
+ self.responseFromCache.master = ruby_system.network.slave
+ self.forwardToCache = MessageBuffer(ordered = True)
+ self.forwardToCache.slave = ruby_system.network.master
+ self.responseToCache = MessageBuffer(ordered = True)
+ self.responseToCache.slave = ruby_system.network.master
+
+class DirController(Directory_Controller):
+
+ _version = 0
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
+ def __init__(self, ruby_system, ranges, mem_ctrls):
+ """ranges are the memory ranges assigned to this controller.
+ """
+ if len(mem_ctrls) > 1:
+ panic("This cache system can only be connected to one mem
ctrl")
+ super(DirController, self).__init__()
+ self.version = self.versionCount()
+ self.addr_ranges = ranges
+ self.ruby_system = ruby_system
+ self.directory = RubyDirectoryMemory()
+ # Connect this directory to the memory side.
+ self.memory = mem_ctrls[0].port
+ self.connectQueues(ruby_system)
+
+ def connectQueues(self, ruby_system):
+ self.requestToDir = MessageBuffer(ordered = True)
+ self.requestToDir.slave = ruby_system.network.master
+ self.dmaRequestToDir = MessageBuffer(ordered = True)
+ self.dmaRequestToDir.slave = ruby_system.network.master
+
+ self.responseFromDir = MessageBuffer()
+ self.responseFromDir.master = ruby_system.network.slave
+ self.dmaResponseFromDir = MessageBuffer(ordered = True)
+ self.dmaResponseFromDir.master = ruby_system.network.slave
+ self.forwardFromDir = MessageBuffer()
+ self.forwardFromDir.master = ruby_system.network.slave
+ self.responseFromMemory = MessageBuffer()
+
+class DMAController(DMA_Controller):
+
+ _version = 0
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
+ def __init__(self, ruby_system):
+ super(DMAController, self).__init__()
+ self.version = self.versionCount()
+ self.ruby_system = ruby_system
+ self.connectQueues(ruby_system)
+
+ def connectQueues(self, ruby_system):
+ self.mandatoryQueue = MessageBuffer()
+ self.requestToDir = MessageBuffer()
+ self.requestToDir.master = ruby_system.network.slave
+ self.responseFromDir = MessageBuffer(ordered = True)
+ self.responseFromDir.slave = ruby_system.network.master
+
+
+class MyNetwork(SimpleNetwork):
+ """A simple point-to-point network. This doesn't not use garnet.
+ """
+
+ def __init__(self, ruby_system):
+ super(MyNetwork, self).__init__()
+ self.netifs = []
+ self.ruby_system = ruby_system
+
+ def connectControllers(self, controllers):
+ """Connect all of the controllers to routers and connec the routers
+ together in a point-to-point network.
+ """
+ # Create one router/switch per controller in the system
+ self.routers = [Switch(router_id = i) for i in
range(len(controllers))]
+
+ # Make a link from each controller to the router. The link goes
+ # externally to the network.
+ self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
+ int_node=self.routers[i])
+ for i, c in enumerate(controllers)]
+
+ # Make an "internal" link (internal to the network) between every
pair
+ # of routers.
+ link_count = 0
+ self.int_links = []
+ for ri in self.routers:
+ for rj in self.routers:
+ if ri == rj: continue # Don't connect a router to itself!
+ link_count += 1
+ self.int_links.append(SimpleIntLink(link_id = link_count,
+ src_node = ri,
+ dst_node = rj))
diff --git a/tests/gem5/boot-tests/system/__init__.py
b/tests/gem5/boot-tests/system/__init__.py
new file mode 100755
index 0000000..e90832c
--- /dev/null
+++ b/tests/gem5/boot-tests/system/__init__.py
@@ -0,0 +1,31 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+from system import MySystem
+from ruby_system import MyRubySystem
\ No newline at end of file
diff --git a/tests/gem5/boot-tests/system/caches.py
b/tests/gem5/boot-tests/system/caches.py
new file mode 100755
index 0000000..4630cea
--- /dev/null
+++ b/tests/gem5/boot-tests/system/caches.py
@@ -0,0 +1,202 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+""" Caches with options for a simple gem5 configuration script
+
+This file contains L1 I/D and L2 caches to be used in the simple
+gem5 configuration script. It uses the SimpleOpts wrapper to set up command
+line options from each individual class.
+"""
+
+import m5
+from m5.objects import Cache, L2XBar, StridePrefetcher, SubSystem
+from m5.params import AddrRange, AllMemory, MemorySize
+from m5.util.convert import toMemorySize
+
+import SimpleOpts
+
+# Some specific options for caches
+# For all options see src/mem/cache/BaseCache.py
+
+class PrefetchCache(Cache):
+
+ SimpleOpts.add_option("--no_prefetchers", default=False,
+ action="store_true",
+ help="Enable prefectchers on the caches")
+
+ def __init__(self, options):
+ super(PrefetchCache, self).__init__()
+ if not options or options.no_prefetchers:
+ return
+ self.prefetcher = StridePrefetcher()
+
+class L1Cache(PrefetchCache):
+ """Simple L1 Cache with default values"""
+
+ assoc = 8
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 16
+ tgts_per_mshr = 20
+ writeback_clean = True
+
+ def __init__(self, options=None):
+ super(L1Cache, self).__init__(options)
+ pass
+
+ def connectBus(self, bus):
+ """Connect this cache to a memory-side bus"""
+ self.mem_side = bus.slave
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU-side port
+ This must be defined in a subclass"""
+ raise NotImplementedError
+
+class L1ICache(L1Cache):
+ """Simple L1 instruction cache with default values"""
+
+ # Set the default size
+ size = '32kB'
+
+ SimpleOpts.add_option('--l1i_size',
+ help="L1 instruction cache size. Default: %s" %
size)
+
+ def __init__(self, opts=None):
+ super(L1ICache, self).__init__(opts)
+ if not opts or not opts.l1i_size:
+ return
+ self.size = opts.l1i_size
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU icache port"""
+ self.cpu_side = cpu.icache_port
+
+class L1DCache(L1Cache):
+ """Simple L1 data cache with default values"""
+
+ # Set the default size
+ size = '32kB'
+
+ SimpleOpts.add_option('--l1d_size',
+ help="L1 data cache size. Default: %s" % size)
+
+ def __init__(self, opts=None):
+ super(L1DCache, self).__init__(opts)
+ if not opts or not opts.l1d_size:
+ return
+ self.size = opts.l1d_size
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU dcache port"""
+ self.cpu_side = cpu.dcache_port
+
+class MMUCache(Cache):
+ # Default parameters
+ size = '8kB'
+ assoc = 4
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 20
+ tgts_per_mshr = 12
+ writeback_clean = True
+
+ def __init__(self):
+ super(MMUCache, self).__init__()
+
+ def connectCPU(self, cpu):
+ """Connect the CPU itb and dtb to the cache
+ Note: This creates a new crossbar
+ """
+ self.mmubus = L2XBar()
+ self.cpu_side = self.mmubus.master
+ for tlb in [cpu.itb, cpu.dtb]:
+ self.mmubus.slave = tlb.walker.port
+
+ def connectBus(self, bus):
+ """Connect this cache to a memory-side bus"""
+ self.mem_side = bus.slave
+
+class L2Cache(PrefetchCache):
+ """Simple L2 Cache with default values"""
+
+ # Default parameters
+ size = '256kB'
+ assoc = 16
+ tag_latency = 10
+ data_latency = 10
+ response_latency = 1
+ mshrs = 20
+ tgts_per_mshr = 12
+ writeback_clean = True
+
+ SimpleOpts.add_option('--l2_size',
+ help="L2 cache size. Default: %s" % size)
+
+ def __init__(self, opts=None):
+ super(L2Cache, self).__init__(opts)
+ if not opts or not opts.l2_size:
+ return
+ self.size = opts.l2_size
+
+ def connectCPUSideBus(self, bus):
+ self.cpu_side = bus.master
+
+ def connectMemSideBus(self, bus):
+ self.mem_side = bus.slave
+
+class L3Cache(Cache):
+ """Simple L3 Cache bank with default values
+ This assumes that the L3 is made up of multiple banks. This cannot
+ be used as a standalone L3 cache.
+ """
+
+ SimpleOpts.add_option('--l3_size', default = '4MB',
+ help="L3 cache size. Default: 4MB")
+
+ # Default parameters
+ assoc = 32
+ tag_latency = 40
+ data_latency = 40
+ response_latency = 10
+ mshrs = 256
+ tgts_per_mshr = 12
+ clusivity = 'mostly_excl'
+
+ def __init__(self, opts):
+ super(L3Cache, self).__init__()
+ self.size = (opts.l3_size)
+
+ def connectCPUSideBus(self, bus):
+ self.cpu_side = bus.master
+
+ def connectMemSideBus(self, bus):
+ self.mem_side = bus.slave
diff --git a/tests/gem5/boot-tests/system/fs_tools.py
b/tests/gem5/boot-tests/system/fs_tools.py
new file mode 100755
index 0000000..22a43d2
--- /dev/null
+++ b/tests/gem5/boot-tests/system/fs_tools.py
@@ -0,0 +1,39 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+from m5.objects import IdeDisk, CowDiskImage, RawDiskImage
+
+class CowDisk(IdeDisk):
+
+ def __init__(self, filename):
+ super(CowDisk, self).__init__()
+ self.driveID = 'master'
+ self.image = CowDiskImage(child=RawDiskImage(read_only=True),
+ read_only=False)
+ self.image.child.image_file = filename
diff --git a/tests/gem5/boot-tests/system/ruby_system.py
b/tests/gem5/boot-tests/system/ruby_system.py
new file mode 100755
index 0000000..3fcf62c
--- /dev/null
+++ b/tests/gem5/boot-tests/system/ruby_system.py
@@ -0,0 +1,224 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+import m5
+from m5.objects import *
+from m5.util import convert
+from fs_tools import *
+from MI_example_caches import MyCacheSystem
+
+class MyRubySystem(LinuxX86System):
+
+ def __init__(self, kernel, disk, cpu_type, num_cpus, opts):
+ super(MyRubySystem, self).__init__()
+ self._opts = opts
+
+ self._host_parallel = cpu_type == "kvm"
+
+ # Set up the clock domain and the voltage domain
+ self.clk_domain = SrcClockDomain()
+ self.clk_domain.clock = '3GHz'
+ self.clk_domain.voltage_domain = VoltageDomain()
+
+ self.mem_ranges = [AddrRange(Addr('3GB')), # All data
+ AddrRange(0xC0000000, size=0x100000), # For I/0
+ ]
+
+ self.initFS(num_cpus)
+
+ # Replace these paths with the path to your disk images.
+ # The first disk is the root disk. The second could be used for
swap
+ # or anything else.
+ self.setDiskImages(disk, disk)
+
+ # Change this path to point to the kernel you want to use
+ self.kernel = kernel
+ # Options specified on the kernel command line
+ boot_options =
['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
+ 'root=/dev/hda1']
+
+ self.boot_osflags = ' '.join(boot_options)
+
+ # Create the CPUs for our system.
+ self.createCPU(cpu_type, num_cpus)
+
+ self.createMemoryControllersDDR3()
+
+ # Create the cache hierarchy for the system.
+ self.caches = MyCacheSystem()
+ self.caches.setup(self, self.cpu, self.mem_cntrls,
+ [self.pc.south_bridge.ide.dma,
self.iobus.master],
+ self.iobus)
+
+ if self._host_parallel:
+ # To get the KVM CPUs to run on different host CPUs
+ # Specify a different event queue for each CPU
+ for i,cpu in enumerate(self.cpu):
+ for obj in cpu.descendants():
+ obj.eventq_index = 0
+ cpu.eventq_index = i + 1
+
+ def getHostParallel(self):
+ return self._host_parallel
+
+ def totalInsts(self):
+ return sum([cpu.totalInsts() for cpu in self.cpu])
+
+ def createCPU(self, cpu_type, num_cpus):
+ if cpu_type == "atomic":
+ self.cpu = [AtomicSimpleCPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.mem_mode = 'atomic'
+ elif cpu_type == "kvm":
+ # Note KVM needs a VM and atomic_noncaching
+ self.cpu = [X86KvmCPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.kvm_vm = KvmVM()
+ self.mem_mode = 'atomic_noncaching'
+ elif cpu_type == "o3":
+ self.cpu = [DerivO3CPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.mem_mode = 'timing'
+ elif cpu_type == "simple":
+ self.cpu = [TimingSimpleCPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.mem_mode = 'timing'
+ else:
+ m5.fatal("No CPU type {}".format(cpu_type))
+
+ map(lambda c: c.createThreads(), self.cpu)
+ map(lambda c: c.createInterruptController(), self.cpu)
+
+ def setDiskImages(self, img_path_1, img_path_2):
+ disk0 = CowDisk(img_path_1)
+ disk2 = CowDisk(img_path_2)
+ self.pc.south_bridge.ide.disks = [disk0, disk2]
+
+ def createMemoryControllersDDR3(self):
+ self._createMemoryControllers(1, DDR3_1600_8x8)
+
+ def _createMemoryControllers(self, num, cls):
+ self.mem_cntrls = [
+ cls(range = self.mem_ranges[0])
+ for i in range(num)
+ ]
+
+ def initFS(self, cpus):
+ self.pc = Pc()
+
+ # North Bridge
+ self.iobus = IOXBar()
+
+ # connect the io bus
+ # Note: pass in a reference to where Ruby will connect to in the
future
+ # so the port isn't connected twice.
+ self.pc.attachIO(self.iobus, [self.pc.south_bridge.ide.dma])
+
+ self.intrctrl = IntrControl()
+
+ ###############################################
+
+ # Add in a Bios information structure.
+ self.smbios_table.structures = [X86SMBiosBiosInformation()]
+
+ # Set up the Intel MP table
+ base_entries = []
+ ext_entries = []
+ for i in range(cpus):
+ bp = X86IntelMPProcessor(
+ local_apic_id = i,
+ local_apic_version = 0x14,
+ enable = True,
+ bootstrap = (i ==0))
+ base_entries.append(bp)
+ io_apic = X86IntelMPIOAPIC(
+ id = cpus,
+ version = 0x11,
+ enable = True,
+ address = 0xfec00000)
+ self.pc.south_bridge.io_apic.apic_id = io_apic.id
+ base_entries.append(io_apic)
+ pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
+ base_entries.append(pci_bus)
+ isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
+ base_entries.append(isa_bus)
+ connect_busses = X86IntelMPBusHierarchy(bus_id=1,
+ subtractive_decode=True, parent_bus=0)
+ ext_entries.append(connect_busses)
+ pci_dev4_inta = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 0,
+ source_bus_irq = 0 + (4 << 2),
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 16)
+ base_entries.append(pci_dev4_inta)
+ def assignISAInt(irq, apicPin):
+ assign_8259_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'ExtInt',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 1,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 0)
+ base_entries.append(assign_8259_to_apic)
+ assign_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 1,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = apicPin)
+ base_entries.append(assign_to_apic)
+ assignISAInt(0, 2)
+ assignISAInt(1, 1)
+ for i in range(3, 15):
+ assignISAInt(i, i)
+ self.intel_mp_table.base_entries = base_entries
+ self.intel_mp_table.ext_entries = ext_entries
+
+ entries = \
+ [
+ # Mark the first megabyte of memory as reserved
+ X86E820Entry(addr = 0, size = '639kB', range_type = 1),
+ X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
+ # Mark the rest of physical memory as available
+ X86E820Entry(addr = 0x100000,
+ size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
+ range_type = 1),
+ ]
+
+ # Reserve the last 16kB of the 32-bit address space for m5ops
+ entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
+ range_type=2))
+
+ self.e820_table.entries = entries
diff --git a/tests/gem5/boot-tests/system/system.py
b/tests/gem5/boot-tests/system/system.py
new file mode 100755
index 0000000..d57e909
--- /dev/null
+++ b/tests/gem5/boot-tests/system/system.py
@@ -0,0 +1,318 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+import m5
+from m5.objects import *
+from m5.util import convert
+from fs_tools import *
+from caches import *
+
+class MySystem(LinuxX86System):
+
+ def __init__(self, kernel, disk, cpu_type, num_cpus, opts):
+ super(MySystem, self).__init__()
+ self._opts = opts
+
+ self._host_parallel = cpu_type == "kvm"
+
+ # Set up the clock domain and the voltage domain
+ self.clk_domain = SrcClockDomain()
+ self.clk_domain.clock = '3GHz'
+ self.clk_domain.voltage_domain = VoltageDomain()
+
+ self.mem_ranges = [AddrRange(Addr('3GB')), # All data
+ AddrRange(0xC0000000, size=0x100000), # For I/0
+ ]
+
+ # Create the main memory bus
+ # This connects to main memory
+ self.membus = SystemXBar(width = 64) # 64-byte width
+ self.membus.badaddr_responder = BadAddr()
+ self.membus.default = Self.badaddr_responder.pio
+
+ # Set up the system port for functional access from the simulator
+ self.system_port = self.membus.slave
+
+ self.initFS(self.membus, num_cpus)
+
+ # Replace these paths with the path to your disk images.
+ # The first disk is the root disk. The second could be used for
swap
+ # or anything else.
+ self.setDiskImages(disk, disk)
+
+ # Change this path to point to the kernel you want to use
+ self.kernel = kernel
+ # Options specified on the kernel command line
+ boot_options =
['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=7999923',
+ 'root=/dev/hda1']
+
+ self.boot_osflags = ' '.join(boot_options)
+
+ # Create the CPUs for our system.
+ self.createCPU(cpu_type, num_cpus)
+
+ # Create the cache heirarchy for the system.
+ self.createCacheHierarchy()
+
+ # Set up the interrupt controllers for the system (x86 specific)
+ self.setupInterrupts()
+
+ self.createMemoryControllersDDR3()
+
+ if self._host_parallel:
+ # To get the KVM CPUs to run on different host CPUs
+ # Specify a different event queue for each CPU
+ for i,cpu in enumerate(self.cpu):
+ for obj in cpu.descendants():
+ obj.eventq_index = 0
+ cpu.eventq_index = i + 1
+
+ def getHostParallel(self):
+ return self._host_parallel
+
+ def totalInsts(self):
+ return sum([cpu.totalInsts() for cpu in self.cpu])
+
+ def createCPU(self, cpu_type, num_cpus):
+ if cpu_type == "atomic":
+ self.cpu = [AtomicSimpleCPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.mem_mode = 'atomic'
+ elif cpu_type == "kvm":
+ # Note KVM needs a VM and atomic_noncaching
+ self.cpu = [X86KvmCPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.kvm_vm = KvmVM()
+ self.mem_mode = 'atomic_noncaching'
+ elif cpu_type == "o3":
+ self.cpu = [DerivO3CPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.mem_mode = 'timing'
+ elif cpu_type == "simple":
+ self.cpu = [TimingSimpleCPU(cpu_id = i)
+ for i in range(num_cpus)]
+ self.mem_mode = 'timing'
+ else:
+ m5.fatal("No CPU type {}".format(cpu_type))
+
+ map(lambda c: c.createThreads(), self.cpu)
+
+ def setDiskImages(self, img_path_1, img_path_2):
+ disk0 = CowDisk(img_path_1)
+ disk2 = CowDisk(img_path_2)
+ self.pc.south_bridge.ide.disks = [disk0, disk2]
+
+ def createCacheHierarchy(self):
+ for cpu in self.cpu:
+ # Create a memory bus, a coherent crossbar, in this case
+ cpu.l2bus = L2XBar()
+
+ # Create an L1 instruction and data cache
+ cpu.icache = L1ICache(self._opts)
+ cpu.dcache = L1DCache(self._opts)
+ cpu.mmucache = MMUCache()
+
+ # Connect the instruction and data caches to the CPU
+ cpu.icache.connectCPU(cpu)
+ cpu.dcache.connectCPU(cpu)
+ cpu.mmucache.connectCPU(cpu)
+
+ # Hook the CPU ports up to the l2bus
+ cpu.icache.connectBus(cpu.l2bus)
+ cpu.dcache.connectBus(cpu.l2bus)
+ cpu.mmucache.connectBus(cpu.l2bus)
+
+ # Create an L2 cache and connect it to the l2bus
+ cpu.l2cache = L2Cache(self._opts)
+ cpu.l2cache.connectCPUSideBus(cpu.l2bus)
+
+ # Connect the L2 cache to the L3 bus
+ cpu.l2cache.connectMemSideBus(self.membus)
+
+ def setupInterrupts(self):
+ for cpu in self.cpu:
+ # create the interrupt controller CPU and connect to the membus
+ cpu.createInterruptController()
+
+ # For x86 only, connect interrupts to the memory
+ # Note: these are directly connected to the memory bus and
+ # not cached
+ cpu.interrupts[0].pio = self.membus.master
+ cpu.interrupts[0].int_master = self.membus.slave
+ cpu.interrupts[0].int_slave = self.membus.master
+
+
+ def createMemoryControllersDDR3(self):
+ self._createMemoryControllers(1, DDR3_1600_8x8)
+
+ def _createMemoryControllers(self, num, cls):
+ self.mem_cntrls = [
+ cls(range = self.mem_ranges[0],
+ port = self.membus.master)
+ for i in range(num)
+ ]
+
+ def initFS(self, membus, cpus):
+ self.pc = Pc()
+
+ # Constants similar to x86_traits.hh
+ IO_address_space_base = 0x8000000000000000
+ pci_config_address_space_base = 0xc000000000000000
+ interrupts_address_space_base = 0xa000000000000000
+ APIC_range_size = 1 << 12;
+
+ # North Bridge
+ self.iobus = IOXBar()
+ self.bridge = Bridge(delay='50ns')
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = membus.master
+ # Allow the bridge to pass through:
+ # 1) kernel configured PCI device memory map address: address
range
+ # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for
m5ops.)
+ # 2) the bridge to pass through the IO APIC (two pages, already
+ # contained in 1),
+ # 3) everything in the IO address range up to the local APIC, and
+ # 4) then the entire PCI address space and beyond.
+ self.bridge.ranges = \
+ [
+ AddrRange(0xC0000000, 0xFFFF0000),
+ AddrRange(IO_address_space_base,
+ interrupts_address_space_base - 1),
+ AddrRange(pci_config_address_space_base,
+ Addr.max)
+ ]
+
+ # Create a bridge from the IO bus to the memory bus to allow access
+ # to the local APIC (two pages)
+ self.apicbridge = Bridge(delay='50ns')
+ self.apicbridge.slave = self.iobus.master
+ self.apicbridge.master = membus.slave
+ self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
+ interrupts_address_space_base +
+ cpus * APIC_range_size
+ - 1)]
+
+ # connect the io bus
+ self.pc.attachIO(self.iobus)
+
+ # Add a tiny cache to the IO bus.
+ # This cache is required for the classic memory model for coherence
+ self.iocache = Cache(assoc=8,
+ tag_latency = 50,
+ data_latency = 50,
+ response_latency = 50,
+ mshrs = 20,
+ size = '1kB',
+ tgts_per_mshr = 12,
+ addr_ranges = self.mem_ranges)
+ self.iocache.cpu_side = self.iobus.master
+ self.iocache.mem_side = self.membus.slave
+
+ self.intrctrl = IntrControl()
+
+ ###############################################
+
+ # Add in a Bios information structure.
+ self.smbios_table.structures = [X86SMBiosBiosInformation()]
+
+ # Set up the Intel MP table
+ base_entries = []
+ ext_entries = []
+ for i in range(cpus):
+ bp = X86IntelMPProcessor(
+ local_apic_id = i,
+ local_apic_version = 0x14,
+ enable = True,
+ bootstrap = (i ==0))
+ base_entries.append(bp)
+ io_apic = X86IntelMPIOAPIC(
+ id = cpus,
+ version = 0x11,
+ enable = True,
+ address = 0xfec00000)
+ self.pc.south_bridge.io_apic.apic_id = io_apic.id
+ base_entries.append(io_apic)
+ pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ')
+ base_entries.append(pci_bus)
+ isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ')
+ base_entries.append(isa_bus)
+ connect_busses = X86IntelMPBusHierarchy(bus_id=1,
+ subtractive_decode=True, parent_bus=0)
+ ext_entries.append(connect_busses)
+ pci_dev4_inta = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 0,
+ source_bus_irq = 0 + (4 << 2),
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 16)
+ base_entries.append(pci_dev4_inta)
+ def assignISAInt(irq, apicPin):
+ assign_8259_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'ExtInt',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 1,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 0)
+ base_entries.append(assign_8259_to_apic)
+ assign_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 1,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = apicPin)
+ base_entries.append(assign_to_apic)
+ assignISAInt(0, 2)
+ assignISAInt(1, 1)
+ for i in range(3, 15):
+ assignISAInt(i, i)
+ self.intel_mp_table.base_entries = base_entries
+ self.intel_mp_table.ext_entries = ext_entries
+
+ entries = \
+ [
+ # Mark the first megabyte of memory as reserved
+ X86E820Entry(addr = 0, size = '639kB', range_type = 1),
+ X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
+ # Mark the rest of physical memory as available
+ X86E820Entry(addr = 0x100000,
+ size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
+ range_type = 1),
+ ]
+
+ # Reserve the last 16kB of the 32-bit address space for m5ops
+ entries.append(X86E820Entry(addr = 0xFFFF0000, size = '64kB',
+ range_type=2))
+
+ self.e820_table.entries = entries
diff --git a/tests/gem5/boot-tests/test_linux_boot.py
b/tests/gem5/boot-tests/test_linux_boot.py
new file mode 100644
index 0000000..add42f0
--- /dev/null
+++ b/tests/gem5/boot-tests/test_linux_boot.py
@@ -0,0 +1,65 @@
+# Copyright (c) 2020 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from testlib import *
+
+cpu_types = ('atomic', 'simple',)
+
+num_cpus = '1'
+
+if config.bin_path:
+ base_path = config.bin_path
+else:
+ base_path = joinpath(absdirpath(__file__), '..', 'resources',
+ 'ubuntu-boot')
+
+image_url = 'http://dist.gem5.org/images/x86/ubuntu-18-04/base.img'
+kernel_url = 'http://dist.gem5.org/kernels/x86/static/vmlinux-5.2.3'
+
+image_name = 'ubuntu-18-04-base.img'
+kernel_name = 'vmlinux-5.2.3'
+
+image = DownloadedProgram(image_url, base_path, image_name)
+kernel = DownloadedProgram(kernel_url, base_path, kernel_name)
+
+for cpu_type in cpu_types:
+ gem5_verify_config(
+ name = 'test-ubuntu_boot-' + cpu_type,
+ verifiers = (),
+ fixtures = (image, kernel,),
+ config = joinpath(joinpath(absdirpath(__file__), 'run_exit.py')),
+ config_args = [
+ joinpath(base_path, kernel_name), # kernel
+ joinpath(base_path, image_name), # disk
+ cpu_type, # cpu_type
+ 'classic', # mem_sys
+ num_cpus, # num_cpus
+ 'systemd', # boot_type
+ ],
+ valid_isas = ('X86',),
+ valid_hosts = constants.supported_hosts,
+ length = constants.long_tag,
+ )
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/26324
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I81385b5dfc0764af2ec02999eb26e523bd09a595
Gerrit-Change-Number: 26324
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
