Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/26546 )
Change subject: arm: Eliminate the MustBeOne ARM specific request flag.
......................................................................
arm: Eliminate the MustBeOne ARM specific request flag.
This flag makes constructing a generic Request object for ARM
impossible, since generic consumers won't know to set that flag to one.
As a principle, Request flags should change the behavior of a request
away from whatever the default/typical behavior is in the current
context, so flags set to zero means no special behavior.
Change-Id: Id606dc0bf42210218e1745585327671a98a8dba4
---
M src/arch/arm/insts/macromem.cc
M src/arch/arm/insts/macromem.hh
M src/arch/arm/insts/sve_mem.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa/formats/fp.isa
M src/arch/arm/isa/insts/amo64.isa
M src/arch/arm/isa/insts/branch.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/str.isa
M src/arch/arm/isa/insts/str64.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tracers/tarmac_parser.cc
18 files changed, 47 insertions(+), 87 deletions(-)
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 125e0f8..211a176 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -472,7 +472,7 @@
RegIndex rMid = deinterleave ? VecSpecialElem : vd * 2;
- uint32_t noAlign = TLB::MustBeOne;
+ uint32_t noAlign = 0;
unsigned uopIdx = 0;
switch (regs) {
@@ -833,7 +833,7 @@
if (interleave) numMicroops += (regs / elems);
microOps = new StaticInstPtr[numMicroops];
- uint32_t noAlign = TLB::MustBeOne;
+ uint32_t noAlign = 0;
RegIndex rMid = interleave ? VecSpecialElem : vd * 2;
@@ -1143,8 +1143,7 @@
microOps = new StaticInstPtr[numMicroops];
unsigned uopIdx = 0;
- uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
- TLB::AllowUnaligned;
+ uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
int i = 0;
for (; i < numMemMicroops - 1; ++i) {
@@ -1251,8 +1250,7 @@
}
}
- uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
- TLB::AllowUnaligned;
+ uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
int i = 0;
for (; i < numMemMicroops - 1; ++i) {
@@ -1319,8 +1317,7 @@
microOps = new StaticInstPtr[numMicroops];
unsigned uopIdx = 0;
- uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
- TLB::AllowUnaligned;
+ uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
int i = 0;
for (; i < numMemMicroops - 1; ++i) {
@@ -1398,8 +1395,7 @@
numStructElems, index, i /* step */, replicate);
}
- uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
- TLB::AllowUnaligned;
+ uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
int i = 0;
for (; i < numMemMicroops - 1; ++i) {
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index b3ba76d..94a3e0f 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -118,8 +118,7 @@
MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass
__opClass,
RegIndex _dest, RegIndex _ura, uint32_t _imm)
: MicroOp(mnem, machInst, __opClass),
- dest(_dest), ura(_ura), imm(_imm),
- memAccessFlags(TLB::MustBeOne)
+ dest(_dest), ura(_ura), imm(_imm), memAccessFlags()
{
}
};
@@ -393,7 +392,7 @@
MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
: MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
- up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
+ up(_up), memAccessFlags(TLB::AlignWord)
{
}
@@ -414,7 +413,7 @@
bool _up, uint8_t _imm)
: MicroOp(mnem, machInst, __opClass),
dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
- memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
+ memAccessFlags(TLB::AlignWord)
{
}
diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh
index 7625374..4865113 100644
--- a/src/arch/arm/insts/sve_mem.hh
+++ b/src/arch/arm/insts/sve_mem.hh
@@ -61,7 +61,7 @@
IntRegIndex _base, uint64_t _imm)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), base(_base), imm(_imm),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
baseIsSP = isSP(_base);
}
@@ -86,7 +86,7 @@
IntRegIndex _base, uint64_t _imm)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), base(_base), imm(_imm),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
baseIsSP = isSP(_base);
}
@@ -112,7 +112,7 @@
IntRegIndex _offset)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), base(_base), offset(_offset),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
baseIsSP = isSP(_base);
}
@@ -138,7 +138,7 @@
uint64_t _imm)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), base(_base), imm(_imm),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
baseIsSP = isSP(_base);
}
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b2175cb..2cc0f95 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1680,60 +1680,54 @@
Fault fault;
switch(misc_reg) {
case MISCREG_ATS1CPR:
- flags = TLB::MustBeOne;
tranType = TLB::S1CTran;
mode = BaseTLB::Read;
break;
case MISCREG_ATS1CPW:
- flags = TLB::MustBeOne;
tranType = TLB::S1CTran;
mode = BaseTLB::Write;
break;
case MISCREG_ATS1CUR:
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S1CTran;
mode = BaseTLB::Read;
break;
case MISCREG_ATS1CUW:
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S1CTran;
mode = BaseTLB::Write;
break;
case MISCREG_ATS12NSOPR:
if (!haveSecurity)
panic("Security Extensions required for ATS12NSOPR");
- flags = TLB::MustBeOne;
tranType = TLB::S1S2NsTran;
mode = BaseTLB::Read;
break;
case MISCREG_ATS12NSOPW:
if (!haveSecurity)
panic("Security Extensions required for ATS12NSOPW");
- flags = TLB::MustBeOne;
tranType = TLB::S1S2NsTran;
mode = BaseTLB::Write;
break;
case MISCREG_ATS12NSOUR:
if (!haveSecurity)
panic("Security Extensions required for ATS12NSOUR");
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S1S2NsTran;
mode = BaseTLB::Read;
break;
case MISCREG_ATS12NSOUW:
if (!haveSecurity)
panic("Security Extensions required for ATS12NSOUW");
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S1S2NsTran;
mode = BaseTLB::Write;
break;
case MISCREG_ATS1HR: // only really useful from secure
mode.
- flags = TLB::MustBeOne;
tranType = TLB::HypMode;
mode = BaseTLB::Read;
break;
case MISCREG_ATS1HW:
- flags = TLB::MustBeOne;
tranType = TLB::HypMode;
mode = BaseTLB::Write;
break;
@@ -1947,62 +1941,54 @@
Fault fault;
switch(misc_reg) {
case MISCREG_AT_S1E1R_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S1E1Tran;
mode = BaseTLB::Read;
break;
case MISCREG_AT_S1E1W_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S1E1Tran;
mode = BaseTLB::Write;
break;
case MISCREG_AT_S1E0R_Xt:
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S1E0Tran;
mode = BaseTLB::Read;
break;
case MISCREG_AT_S1E0W_Xt:
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S1E0Tran;
mode = BaseTLB::Write;
break;
case MISCREG_AT_S1E2R_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S1E2Tran;
mode = BaseTLB::Read;
break;
case MISCREG_AT_S1E2W_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S1E2Tran;
mode = BaseTLB::Write;
break;
case MISCREG_AT_S12E0R_Xt:
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S12E0Tran;
mode = BaseTLB::Read;
break;
case MISCREG_AT_S12E0W_Xt:
- flags = TLB::MustBeOne | TLB::UserMode;
+ flags = TLB::UserMode;
tranType = TLB::S12E0Tran;
mode = BaseTLB::Write;
break;
case MISCREG_AT_S12E1R_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S12E1Tran;
mode = BaseTLB::Read;
break;
case MISCREG_AT_S12E1W_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S12E1Tran;
mode = BaseTLB::Write;
break;
case MISCREG_AT_S1E3R_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S1E3Tran;
mode = BaseTLB::Read;
break;
case MISCREG_AT_S1E3W_Xt:
- flags = TLB::MustBeOne;
tranType = TLB::S1E3Tran;
mode = BaseTLB::Write;
break;
diff --git a/src/arch/arm/isa/formats/fp.isa
b/src/arch/arm/isa/formats/fp.isa
index 0b99cc6..de0fdd2 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -141,7 +141,7 @@
bits(machInst, 22) << 4);
const uint32_t type = bits(machInst, 11, 8);
uint32_t size = 0;
- uint32_t align = TLB::MustBeOne;
+ uint32_t align = 0;
unsigned inc = 1;
unsigned regs = 1;
unsigned lane = 0;
diff --git a/src/arch/arm/isa/insts/amo64.isa
b/src/arch/arm/isa/insts/amo64.isa
index 86ee7ba..6d3a515 100644
--- a/src/arch/arm/isa/insts/amo64.isa
+++ b/src/arch/arm/isa/insts/amo64.isa
@@ -75,7 +75,7 @@
self.top = top
self.paired = paired
- self.memFlags = ["ArmISA::TLB::MustBeOne"]
+ self.memFlags = []
self.instFlags = ["IsAtomic"]
self.codeBlobs = { "postacc_code" : "" }
self.codeBlobs['usrDecl'] = ""
diff --git a/src/arch/arm/isa/insts/branch.isa
b/src/arch/arm/isa/insts/branch.isa
index 69a220e..f61d0c5 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -188,8 +188,7 @@
if isTbh:
eaCode = '''
unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
- ArmISA::TLB::AlignHalfWord |
- ArmISA::TLB::MustBeOne;
+ ArmISA::TLB::AlignHalfWord;
EA = Op1 + Op2 * 2
'''
accCode = 'NPC = PC + 2 * (Mem_uh);\n'
@@ -197,8 +196,7 @@
else:
eaCode = '''
unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
- ArmISA::TLB::AlignByte |
- ArmISA::TLB::MustBeOne;
+ ArmISA::TLB::AlignByte;
EA = Op1 + Op2
'''
accCode = 'NPC = PC + 2 * (Mem_ub)'
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 16b3c57..3c1e941 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -386,8 +386,7 @@
msrdczva_ea_code = msr_check_code
msrdczva_ea_code += '''
- Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO |
- ArmISA::TLB::MustBeOne;
+ Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO;
EA = XBase;
assert(!(Dczid & 0x10));
uint64_t op_size = power(2, Dczid + 2);
@@ -418,8 +417,7 @@
msrdccvau_ea_code = msr_check_code
msrdccvau_ea_code += '''
- Request::Flags memAccessFlags = Request::CLEAN |
Request::DST_POU |
- ArmISA::TLB::MustBeOne;
+ Request::Flags memAccessFlags = Request::CLEAN |
Request::DST_POU;
EA = XBase;
faultAddr = EA;
System *sys = xc->tcBase()->getSystemPtr();
@@ -443,8 +441,7 @@
msrdccvac_ea_code = msr_check_code
msrdccvac_ea_code += '''
- Request::Flags memAccessFlags = Request::CLEAN |
Request::DST_POC |
- ArmISA::TLB::MustBeOne;
+ Request::Flags memAccessFlags = Request::CLEAN |
Request::DST_POC;
EA = XBase;
faultAddr = EA;
System *sys = xc->tcBase()->getSystemPtr();
@@ -469,7 +466,7 @@
msrdccivac_ea_code = msr_check_code
msrdccivac_ea_code += '''
Request::Flags memAccessFlags = Request::CLEAN |
- Request::INVALIDATE | Request::DST_POC |
ArmISA::TLB::MustBeOne;
+ Request::INVALIDATE | Request::DST_POC;
EA = XBase;
faultAddr = EA;
System *sys = xc->tcBase()->getSystemPtr();
@@ -494,7 +491,7 @@
msrdcivac_ea_code = msr_check_code
msrdcivac_ea_code += '''
Request::Flags memAccessFlags = Request::INVALIDATE |
- Request::DST_POC | ArmISA::TLB::MustBeOne;
+ Request::DST_POC;
EA = XBase;
faultAddr = EA;
HCR hcr = Hcr64;
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index cab3cff..dc1d650 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -64,10 +64,11 @@
else:
self.op = " -"
- self.memFlags = ["ArmISA::TLB::MustBeOne"]
+ self.memFlags = []
self.codeBlobs = {"postacc_code" : ""}
- def emitHelper(self, base = 'Memory', wbDecl = None, instFlags =
[], pcDecl = None):
+ def emitHelper(self, base='Memory', wbDecl=None, instFlags=[],
+ pcDecl=None):
global header_output, decoder_output, exec_output
diff --git a/src/arch/arm/isa/insts/ldr64.isa
b/src/arch/arm/isa/insts/ldr64.isa
index 96bf642..4f12509 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -58,7 +58,7 @@
self.flavor = flavor
self.top = top
- self.memFlags = ["ArmISA::TLB::MustBeOne"]
+ self.memFlags = []
self.instFlags = []
self.codeBlobs = {"postacc_code" : ""}
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 0c6fdc3..f32d733 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1119,8 +1119,7 @@
'''
McrDcimvacCode = '''
- const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
- Request::INVALIDATE |
+ const Request::Flags memAccessFlags(Request::INVALIDATE |
Request::DST_POC);
EA = Op1;
'''
@@ -1138,8 +1137,7 @@
Mcr15CompleteAcc.subst(McrDcimvacIop)
McrDccmvacCode = '''
- const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
- Request::CLEAN |
+ const Request::Flags memAccessFlags(Request::CLEAN |
Request::DST_POC);
EA = Op1;
'''
@@ -1157,8 +1155,7 @@
Mcr15CompleteAcc.subst(McrDccmvacIop)
McrDccmvauCode = '''
- const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
- Request::CLEAN |
+ const Request::Flags memAccessFlags(Request::CLEAN |
Request::DST_POU);
EA = Op1;
'''
@@ -1176,8 +1173,7 @@
Mcr15CompleteAcc.subst(McrDccmvauIop)
McrDccimvacCode = '''
- const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
- Request::CLEAN |
+ const Request::Flags memAccessFlags(Request::CLEAN |
Request::INVALIDATE |
Request::DST_POC);
EA = Op1;
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 38c1ccb..f542478 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -63,7 +63,7 @@
else:
self.op = " -"
- self.memFlags = ["ArmISA::TLB::MustBeOne"]
+ self.memFlags = []
self.codeBlobs = { "postacc_code" : "" }
def emitHelper(self, base = 'Memory', wbDecl = None):
@@ -137,8 +137,7 @@
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
- ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
- 'SrsOp', wbDecl)
+ ["ArmISA::TLB::AlignWord"], [], 'SrsOp', wbDecl)
header_output += newHeader
decoder_output += newDecoder
diff --git a/src/arch/arm/isa/insts/str64.isa
b/src/arch/arm/isa/insts/str64.isa
index 58ca3df..22d1456 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -56,7 +56,7 @@
self.flavor = flavor
self.top = top
- self.memFlags = ["ArmISA::TLB::MustBeOne"]
+ self.memFlags = []
self.instFlags = []
self.codeBlobs = { "postacc_code" : "" }
diff --git a/src/arch/arm/isa/templates/sve_mem.isa
b/src/arch/arm/isa/templates/sve_mem.isa
index bd9cb83..fc31b2d 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -408,8 +408,7 @@
dest(_dest), gp(_gp), base(_base), imm(_imm),
elemIndex(_elemIndex), numElems(_numElems),
firstFault(_firstFault),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
- ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
%(constructor)s;
if (_opClass == MemReadOp && elemIndex == 0) {
@@ -488,8 +487,7 @@
offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned),
offsetIsScaled(_offsetIsScaled), elemIndex(_elemIndex),
numElems(_numElems), firstFault(_firstFault),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
- ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
%(constructor)s;
if (_opClass == MemReadOp && elemIndex == 0) {
@@ -847,8 +845,7 @@
: %(base_class)s(mnem, machInst, %(op_class)s),
dest(_dest), gp(_gp), base(_base), imm(_imm),
numRegs(_numRegs), regIndex(_regIndex),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
- ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
%(constructor)s;
baseIsSP = isSP(_base);
@@ -1111,8 +1108,7 @@
: %(base_class)s(mnem, machInst, %(op_class)s),
dest(_dest), gp(_gp), base(_base), offset(_offset),
numRegs(_numRegs), regIndex(_regIndex),
- memAccessFlags(ArmISA::TLB::AllowUnaligned |
- ArmISA::TLB::MustBeOne)
+ memAccessFlags(ArmISA::TLB::AllowUnaligned)
{
%(constructor)s;
baseIsSP = isSP(_base);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 89eb9c7..51bb8ec 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -2014,7 +2014,6 @@
// check here.
if (currState->stage2Req) {
Fault fault;
- flags = flags | TLB::MustBeOne;
if (isTiming) {
Stage2MMU::Stage2Translation *tran = new
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 31836e1..5a92a0c 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -549,7 +549,6 @@
bool is_write = (mode == Write);
if (!is_fetch) {
- assert(flags & MustBeOne || req->isPrefetch());
if (sctlr.a || !(flags & AllowUnaligned)) {
if (vaddr & mask(flags & AlignmentMask)) {
// LPAE is always disabled in SE mode
@@ -1165,7 +1164,6 @@
req->setFlags(Request::STRICT_ORDER);
}
if (!is_fetch) {
- assert(flags & MustBeOne || req->isPrefetch());
if (sctlr.a || !(flags & AllowUnaligned)) {
if (vaddr & mask(flags & AlignmentMask)) {
alignFaults++;
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 428a445..4efbe02 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -113,11 +113,7 @@
AllowUnaligned = 0x8,
// Priv code operating as if it wasn't
- UserMode = 0x10,
- // Because zero otherwise looks like a valid setting and may be
used
- // accidentally, this bit must be non-zero to show it was used on
- // purpose.
- MustBeOne = 0x40
+ UserMode = 0x10
};
enum ArmTranslationType {
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index 8f1974d..a5fc32d 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -873,8 +873,7 @@
ostream &outs = Trace::output();
uint64_t written_data = 0;
- unsigned mem_flags = ArmISA::TLB::MustBeOne | 3 |
- ArmISA::TLB::AllowUnaligned;
+ unsigned mem_flags = 3 | ArmISA::TLB::AllowUnaligned;
ISetState isetstate;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id606dc0bf42210218e1745585327671a98a8dba4
Gerrit-Change-Number: 26546
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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