Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27711 )
Change subject: arch-arm: Remove unnecessary haveGICv3CPUInterface
......................................................................
arch-arm: Remove unnecessary haveGICv3CPUInterface
This is not needed since the ISA class could just check if
the gicv3CpuInterface ptr is different than nullptr
Change-Id: I6d562a5d9ff2568774b6958f03f04d878266ca8f
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27711
Reviewed-by: Ciro Santilli <ciro.santi...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 5 insertions(+), 7 deletions(-)
Approvals:
Ciro Santilli: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 2cc0f95..a3e0ce6 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -60,7 +60,7 @@
ISA::ISA(Params *p) : BaseISA(p), system(NULL),
_decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
- pmu(p->pmu), haveGICv3CPUInterface(false), impdefAsNop(p->impdef_nop),
+ pmu(p->pmu), impdefAsNop(p->impdef_nop),
afterStartup(false)
{
miscRegs[MISCREG_SCTLR_RST] = 0;
@@ -428,7 +428,6 @@
if (system) {
Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
if (gicv3) {
- haveGICv3CPUInterface = true;
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
gicv3CpuInterface->setISA(this);
gicv3CpuInterface->setThreadContext(tc);
@@ -744,7 +743,7 @@
(haveVirtualization ? 0x0000000000000200 : 0) | // EL2
(haveSecurity ? 0x0000000000002000 : 0) | // EL3
(haveSVE ? 0x0000000100000000 : 0) | // SVE
- (haveGICv3CPUInterface ? 0x0000000001000000 : 0);
+ (gicv3CpuInterface ? 0x0000000001000000 : 0);
case MISCREG_ID_AA64PFR1_EL1:
return 0; // bits [63:0] RES0 (reserved for future use)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 736c395..8f2e0d2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -91,7 +91,6 @@
bool haveVirtualization;
bool haveCrypto;
bool haveLargeAsid64;
- bool haveGICv3CPUInterface;
uint8_t physAddrRange;
bool haveSVE;
bool haveLSE;
@@ -746,14 +745,14 @@
Enums::DecoderFlavor decoderFlavor() const { return
_decoderFlavor; }
- /** Getter for haveGICv3CPUInterface */
+ /** Returns true if the ISA has a GICv3 cpu interface */
bool haveGICv3CpuIfc() const
{
- // haveGICv3CPUInterface is initialized at startup time, hence
+ // gicv3CpuInterface is initialized at startup time, hence
// trying to read its value before the startup stage will lead
// to an error
assert(afterStartup);
- return haveGICv3CPUInterface;
+ return gicv3CpuInterface != nullptr;
}
Enums::VecRegRenameMode
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27711
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6d562a5d9ff2568774b6958f03f04d878266ca8f
Gerrit-Change-Number: 27711
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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