Hello Ciro Santilli,

I'd like you to do a code review. Please visit

    https://gem5-review.googlesource.com/c/public/gem5/+/28450

to review the following change.


Change subject: arch-arm: Decode SEVL instruction for A32 and T32 IS
......................................................................

arch-arm: Decode SEVL instruction for A32 and T32 IS

The instruction had been defined but it was not used for AArch32

Change-Id: I2bb106e98647eaa1f4c71fffb541e76ac1688674
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Ciro Santilli <ciro.santi...@arm.com>
---
M src/arch/arm/isa/formats/branch.isa
M src/arch/arm/isa/formats/data.isa
2 files changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index b7360fc..7c726ef 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010,2012-2013,2017-2018 ARM Limited
+// Copyright (c) 2010,2012-2013,2017-2018, 2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -187,8 +187,7 @@
                                   case 0x4:
                                     return new SevInst(machInst);
                                   case 0x5:
-                                    return new WarnUnimplemented(
-                                            "sevl", machInst);
+                                    return new SevlInst(machInst);
                                 }
                                 break;
                               case 0x1:
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index a927f2b..b742951 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2010,2017-2018 ARM Limited
+// Copyright (c) 2010,2017-2018, 2020 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -1136,8 +1136,7 @@
                       case 0x4:
                         return new SevInst(machInst);
                       case 0x5:
-                        return new WarnUnimplemented(
-                                "sevl", machInst);
+                        return new SevlInst(machInst);
                       case 0x10:
                         return new WarnUnimplemented(
                                 "esb", machInst);
@@ -1283,6 +1282,8 @@
                 return new WfiInst(machInst);
               case 0x4:
                 return new SevInst(machInst);
+              case 0x5:
+                return new SevlInst(machInst);
               default:
                 return new WarnUnimplemented("unallocated_hint", machInst);
             }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28450
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2bb106e98647eaa1f4c71fffb541e76ac1688674
Gerrit-Change-Number: 28450
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-MessageType: newchange
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