Hello kokoro, Juan Manuel Cebrián González, Gabe Black,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28807
to review the following change.
Change subject: Revert "arch-x86,cpu: Fix bpred by annotating branch
instructions in x86"
......................................................................
Revert "arch-x86,cpu: Fix bpred by annotating branch instructions in x86"
This reverts commit 5f0f178651fd5caff05e1a3d15cdd363e08b98e0.
Reason for revert: This should have been on develop.
I didn't notice it was on the master branch.
Change-Id: I670bd86e55f105e555ae49c94733217b2a4327ae
---
M src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
M
src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
M src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
M src/arch/x86/isa/macroop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/isa/microops/seqop.isa
M src/cpu/o3/decode_impl.hh
9 files changed, 6 insertions(+), 113 deletions(-)
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
index edc0007..c58152c 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
@@ -41,7 +41,6 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
- .control_direct
limm t1, imm
rdip t7
@@ -56,7 +55,6 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
- .control_indirect
rdip t1
# Check target of call
@@ -70,7 +68,6 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
- .control_indirect
rdip t7
ld t1, seg, sib, disp
@@ -85,7 +82,6 @@
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_call
- .control_indirect
rdip t7
ld t1, seg, riprel, disp
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
index f92935d..87b2e6a 100644
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
@@ -40,7 +40,6 @@
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -51,7 +50,6 @@
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -62,7 +60,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -73,7 +70,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -84,7 +80,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -95,7 +90,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -106,7 +100,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -117,7 +110,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -128,7 +120,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -139,7 +130,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -150,7 +140,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -161,7 +150,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -172,7 +160,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -183,7 +170,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -194,7 +180,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -205,7 +190,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -214,8 +198,6 @@
def macroop JRCX_I
{
- .control_direct
-
rdip t1
add t0, t0, rcx, flags=(EZF,), dataSize=asz
wripi t1, imm, flags=(CEZF,)
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
index 4d76395..6f419ce 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
@@ -41,7 +41,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_direct
rdip t1
limm t2, imm
@@ -52,7 +51,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_indirect
wripi reg, 0
};
@@ -61,7 +59,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_indirect
ld t1, seg, sib, disp
wripi t1, 0
@@ -71,7 +68,6 @@
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
- .control_indirect
rdip t7
ld t1, seg, riprel, disp
@@ -144,8 +140,6 @@
def macroop JMP_FAR_REAL_M
{
- .control_indirect
-
lea t1, seg, sib, disp, dataSize=asz
ld t2, seg, [1, t0, t1], dsz
ld t1, seg, [1, t0, t1]
@@ -158,14 +152,11 @@
def macroop JMP_FAR_REAL_P
{
- .control_indirect
panic "Real mode far jump executed in 64 bit mode!"
};
def macroop JMP_FAR_REAL_I
{
- .control_indirect
-
# Put the whole far pointer into a register.
limm t2, imm, dataSize=8
# Figure out the width of the offset.
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
index 7ab034e..919551e 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py
@@ -37,8 +37,6 @@
microcode = '''
def macroop LOOP_I {
- .control_direct
-
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
@@ -47,8 +45,6 @@
};
def macroop LOOPNE_I {
- .control_direct
-
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
@@ -57,8 +53,6 @@
};
def macroop LOOPE_I {
- .control_direct
-
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
index 25ddaad..f24b9d7 100644
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
@@ -41,7 +41,6 @@
# Make the default data size of rets 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_return
- .control_indirect
ld t1, ss, [1, t0, rsp]
# Check address of return
@@ -54,7 +53,6 @@
# Make the default data size of rets 64 bits in 64 bit mode
.adjust_env oszIn64Override
.function_return
- .control_indirect
limm t2, imm
ld t1, ss, [1, t0, rsp]
@@ -67,7 +65,6 @@
def macroop RET_FAR {
.adjust_env oszIn64Override
.function_return
- .control_indirect
# Get the return RIP
ld t1, ss, [1, t0, rsp]
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 3a4ccbd..99d76b4 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -153,10 +153,6 @@
self.function_call = True
def function_return(self):
self.function_return = True
- def control_direct(self):
- self.control_direct = True
- def control_indirect(self):
- self.control_indirect = True
def __init__(self, name):
super(X86Macroop, self).__init__(name)
@@ -167,9 +163,7 @@
"serialize_before" : self.serializeBefore,
"serialize_after" : self.serializeAfter,
"function_call" : self.function_call,
- "function_return" : self.function_return,
- "control_direct" : self.control_direct,
- "control_indirect" : self.control_indirect
+ "function_return" : self.function_return
}
self.declared = False
self.adjust_env = ""
@@ -188,8 +182,6 @@
self.serialize_after = False
self.function_call = False
self.function_return = False
- self.control_direct = False
- self.control_indirect = False
def getAllocator(self, env):
return "new X86Macroop::%s(machInst, %s)" % \
@@ -238,10 +230,6 @@
if self.function_return:
flags.append("IsReturn")
flags.append("IsUncondControl")
- if self.control_direct:
- flags.append("IsDirectControl")
- if self.control_indirect:
- flags.append("IsIndirectControl")
else:
flags.append("IsDelayedCommit")
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index 3e393cf..6f2901b 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -112,12 +112,6 @@
uint8_t _dataSize, uint16_t _ext);
Fault execute(ExecContext *, Trace::InstRecord *) const;
-
- X86ISA::PCState branchTarget(const X86ISA::PCState &branchPC) const
- override;
-
- /// Explicitly import the otherwise hidden branchTarget
- using StaticInst::branchTarget;
};
}};
@@ -132,12 +126,6 @@
uint8_t _dataSize, uint16_t _ext);
Fault execute(ExecContext *, Trace::InstRecord *) const;
-
- X86ISA::PCState branchTarget(const X86ISA::PCState &branchPC) const
- override;
-
- /// Explicitly import the otherwise hidden branchTarget
- using StaticInst::branchTarget;
};
}};
@@ -153,17 +141,6 @@
%(constructor)s;
%(cond_control_flag_init)s;
}
-
- X86ISA::PCState
- %(class_name)s::branchTarget(const X86ISA::PCState &branchPC) const
- {
- X86ISA::PCState pcs = branchPC;
- DPRINTF(X86, "branchTarget PC info: %s, Immediate: %lx\n",
- pcs, (int64_t) this->machInst.immediate);
- pcs.npc(pcs.npc() + (int64_t) this->machInst.immediate);
- pcs.uEnd();
- return pcs;
- }
}};
def template MicroRegOpImmConstructor {{
@@ -178,17 +155,6 @@
%(constructor)s;
%(cond_control_flag_init)s;
}
-
- X86ISA::PCState
- %(class_name)s::branchTarget(const X86ISA::PCState &branchPC) const
- {
- X86ISA::PCState pcs = branchPC;
- DPRINTF(X86, "branchTarget PC info: %s, Immediate (imm8): %lx\n",
- pcs, (int8_t)imm8);
- pcs.npc(pcs.npc() + (int8_t)imm8);
- pcs.uEnd();
- return pcs;
- }
}};
output header {{
@@ -309,8 +275,7 @@
# a version without it and fix up this version to use it.
if flag_code != "" or cond_check != "true":
self.buildCppClasses(name, Name, suffix,
- code, big_code, "", "true", else_code,
- "flags[IsUncondControl] = flags[IsControl];",
op_class)
+ code, big_code, "", "true", else_code, "",
op_class)
suffix = "Flags" + suffix
# If psrc1 or psrc2 is used, we need to actually insert code to
diff --git a/src/arch/x86/isa/microops/seqop.isa
b/src/arch/x86/isa/microops/seqop.isa
index 65bf064..f5cb589 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -64,12 +64,6 @@
uint64_t setFlags, uint16_t _target, uint8_t _cc);
Fault execute(ExecContext *, Trace::InstRecord *) const;
-
- X86ISA::PCState branchTarget(const X86ISA::PCState &branchPC) const
- override;
-
- /// Explicitly import the otherwise hidden branchTarget
- using StaticInst::branchTarget;
};
}};
@@ -109,17 +103,6 @@
%(constructor)s;
%(cond_control_flag_init)s;
}
-
- X86ISA::PCState
- %(class_name)s::branchTarget(const X86ISA::PCState &branchPC) const
- {
- X86ISA::PCState pcs = branchPC;
- DPRINTF(X86, "Br branchTarget PC info: %s, Target: %d\n",
- pcs, (int16_t)target);
- pcs.nupc(target);
- pcs.uAdvance();
- return pcs;
- }
}};
output decoder {{
@@ -191,8 +174,7 @@
"else_code": "nuIP = nuIP;",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": "flags[IsCondControl] = true; \
- flags[IsDirectControl] = true;"})
+ "cond_control_flag_init": "flags[IsCondControl] = true"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
@@ -210,8 +192,7 @@
{"code": "", "else_code": "",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": "flags[IsUncondControl] = true;\
- flags[IsDirectControl] = true;"})
+ "cond_control_flag_init": ""})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 561b482..86f9339 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -749,9 +749,8 @@
DPRINTF(Decode,
"[tid:%i] [sn:%llu] "
- "Updating predictions: Wrong predicted target: %s \
- PredPC: %s\n",
- tid, inst->seqNum, inst->readPredTarg(), target);
+ "Updating predictions: PredPC: %s\n",
+ tid, inst->seqNum, target);
//The micro pc after an instruction level branch should be
0
inst->setPredTarg(target);
break;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28807
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I670bd86e55f105e555ae49c94733217b2a4327ae
Gerrit-Change-Number: 28807
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Juan Manuel Cebrián González <jm.cebriangonza...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Trivikram Reddy <tvre...@ucdavis.edu>
Gerrit-MessageType: newchange
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