Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30135 )
Change subject: cpu: Use new InstRecord faulting flag in cpu models
......................................................................
cpu: Use new InstRecord faulting flag in cpu models
This patch sets the faulting flag in atomic, timing, minor and o3 CPU
models.
It also fixes the minor/timing CPU models which were not respecting the
ExecFaulting flag. This is now checked before calling dump() on the
tracing object, to bring it in line with the other CPU models.
Change-Id: I9c7b64cc5605596eb7fcf25fdecaeac5c4b5e3d7
---
M src/cpu/minor/execute.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
6 files changed, 44 insertions(+), 23 deletions(-)
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index ddb8db3..9577549 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014,2018-2019 ARM Limited
+ * Copyright (c) 2013-2014,2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -48,6 +48,7 @@
#include "debug/Activity.hh"
#include "debug/Branch.hh"
#include "debug/Drain.hh"
+#include "debug/ExecFaulting.hh"
#include "debug/MinorExecute.hh"
#include "debug/MinorInterrupt.hh"
#include "debug/MinorMem.hh"
@@ -980,6 +981,15 @@
committed = true;
if (fault != NoFault) {
+ if (inst->traceData) {
+ if (DTRACE(ExecFaulting)) {
+ inst->traceData->setFaulting(true);
+ } else {
+ delete inst->traceData;
+ inst->traceData = NULL;
+ }
+ }
+
DPRINTF(MinorExecute, "Fault in execute of inst: %s
fault: %s\n",
*inst, fault->name());
fault->invoke(thread, inst->staticInst);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 0f65e71..8e8ff6e 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1,6 +1,6 @@
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2014, 2017 ARM Limited
+ * Copyright (c) 2010-2014, 2017, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1260,6 +1260,7 @@
tid, head_inst->seqNum);
if (head_inst->traceData) {
if (DTRACE(ExecFaulting)) {
+ head_inst->traceData->setFaulting(true);
head_inst->traceData->setFetchSeq(head_inst->seqNum);
head_inst->traceData->setCPSeq(thread[tid]->numOp);
head_inst->traceData->dump();
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4671402..c57fe14 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,6 +1,6 @@
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2012-2013,2015,2017-2019 ARM Limited
+ * Copyright (c) 2012-2013,2015,2017-2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -713,10 +713,8 @@
if (fault == NoFault) {
countInst();
ppCommit->notify(std::make_pair(thread,
curStaticInst));
- }
- else if (traceData && !DTRACE(ExecFaulting)) {
- delete traceData;
- traceData = NULL;
+ } else if (traceData) {
+ traceFault();
}
if (fault != NoFault &&
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 8f23bab..d03ae86 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, 2015, 2017, 2018 ARM Limited
+ * Copyright (c) 2010-2012, 2015, 2017, 2018, 2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -433,6 +433,17 @@
}
void
+BaseSimpleCPU::traceFault()
+{
+ if (DTRACE(ExecFaulting)) {
+ traceData->setFaulting(true);
+ } else {
+ delete traceData;
+ traceData = NULL;
+ }
+}
+
+void
BaseSimpleCPU::checkForInterrupts()
{
SimpleExecContext&t_info = *threadInfo[curThread];
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index df17c26..a544211 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012,2015,2018 ARM Limited
+ * Copyright (c) 2011-2012,2015,2018,2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -120,6 +120,14 @@
Status _status;
+ /**
+ * Handler used when encountering a fault; its purpose is to
+ * tear down the InstRecord. If a fault is meant to be traced,
+ * the handler won't delete the record and it will annotate
+ * the record as coming from a faulting instruction.
+ */
+ void traceFault();
+
public:
void checkForInterrupts();
void setupFetchRequest(const RequestPtr &req);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c1c70cb..84d7d0e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,6 +1,6 @@
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited
+ * Copyright (c) 2010-2013,2015,2017-2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -363,10 +363,8 @@
updateCycleCounts();
updateCycleCounters(BaseCPU::CPU_STATE_ON);
- if (traceData) {
- // Since there was a fault, we shouldn't trace this instruction.
- delete traceData;
- traceData = NULL;
+ if ((fault != NoFault) && traceData) {
+ traceFault();
}
postExecute();
@@ -794,9 +792,7 @@
// ifetch
if (_status == BaseSimpleCPU::Running) {
if (fault != NoFault && traceData) {
- // If there was a fault, we shouldn't trace this
instruction.
- delete traceData;
- traceData = NULL;
+ traceFault();
}
postExecute();
@@ -813,9 +809,8 @@
// keep an instruction count
if (fault == NoFault)
countInst();
- else if (traceData && !DTRACE(ExecFaulting)) {
- delete traceData;
- traceData = NULL;
+ else if (traceData) {
+ traceFault();
}
postExecute();
@@ -913,9 +908,7 @@
if (fault == NoFault)
countInst();
else if (traceData) {
- // If there was a fault, we shouldn't trace this instruction.
- delete traceData;
- traceData = NULL;
+ traceFault();
}
delete pkt;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30135
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9c7b64cc5605596eb7fcf25fdecaeac5c4b5e3d7
Gerrit-Change-Number: 30135
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
