Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30322
to review the following change.
Change subject: cpu: Add HTM CPU API
......................................................................
cpu: Add HTM CPU API
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Change-Id: Iff95eb97603b4cb9629c04382a824b02594ee5c7
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/cpu/checker/cpu.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
7 files changed, 68 insertions(+), 4 deletions(-)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd7022..24fad1c 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -434,6 +434,12 @@
thread->setMemAccPredicate(val);
}
+ Fault initiateHtmCmd(Request::Flags flags) override
+ {
+ panic("not yet supported!");
+ return NoFault;
+ }
+
TheISA::PCState pcState() const override { return thread->pcState(); }
void
pcState(const TheISA::PCState &val) override
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b3faf31..79fd1d7 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1833,5 +1833,13 @@
}
}
+template <class Impl>
+void
+FullO3CPU<Impl>::htmSendAbortSignal(ThreadID tid, uint64_t htmUid,
+ HtmFailureFaultCause cause)
+{
+ panic("not yet supported!");
+}
+
// Forward declaration of FullO3CPU.
template class FullO3CPU<O3CPUImpl>;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index c3d911b..61bbdbd 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -788,6 +788,11 @@
//number of misc
Stats::Scalar miscRegfileReads;
Stats::Scalar miscRegfileWrites;
+
+ public:
+ // hardware transactional memory
+ void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
+ HtmFailureFaultCause cause);
};
#endif // __CPU_O3_CPU_HH__
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 53fe0fc..e35cfaa 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015, 2018 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2018-2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -219,6 +219,18 @@
const std::vector<bool>& byte_enable =
std::vector<bool>())
override;
+ Fault initiateHtmCmd(Request::Flags flags) override
+ {
+ panic("initiateHtmCmd() is for timing accesses, and should "
+ "never be called on AtomicSimpleCPU.\n");
+ }
+
+ void htmSendAbortSignal(HtmFailureFaultCause cause) override
+ {
+ panic("htmSendAbortSignal() is for timing accesses, and should "
+ "never be called on AtomicSimpleCPU.\n");
+ }
+
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, Request::Flags flags, uint64_t *res,
const std::vector<bool>& byte_enable =
std::vector<bool>())
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 323850a..b69765b 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012,2015,2018 ARM Limited
+ * Copyright (c) 2011-2012,2015,2018-2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -168,6 +168,21 @@
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
+ /** Hardware transactional memory commands (HtmCmds), e.g. start a
+ * transaction and commit a transaction, are memory operations but are
+ * neither really (true) loads nor stores. For this reason the
interface
+ * is extended and initiateHtmCmd() is used to instigate the command.
*/
+ virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
+
+ /** This function is used to instruct the memory subsystem that a
+ * transaction should be aborted and the speculative state should be
+ * thrown away. This is called in the transaction's very last breath
in
+ * the core. Afterwards, the core throws away its speculative state
and
+ * resumes execution at the point the transaction started, i.e.
reverses
+ * time. When instruction execution resumes, the core expects the
+ * memory subsystem to be in a stable, i.e. pre-speculative, state as
+ * well. */
+ virtual void htmSendAbortSignal(HtmFailureFaultCause cause) = 0;
};
#endif // __CPU_SIMPLE_BASE_HH__
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c1c70cb..a509562 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,6 +1,6 @@
/*
* Copyright 2014 Google, Inc.
- * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited
+ * Copyright (c) 2010-2013,2015,2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1062,6 +1062,19 @@
dcachePort.printAddr(a);
}
+Fault
+TimingSimpleCPU::initiateHtmCmd(Request::Flags flags)
+{
+ panic("not yet supported!");
+ return NoFault;
+}
+
+void
+TimingSimpleCPU::htmSendAbortSignal(HtmFailureFaultCause cause)
+{
+ panic("not yet supported!");
+}
+
////////////////////////////////////////////////////////////////////////
//
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index c8bd05e..59e0197 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013,2015,2018 ARM Limited
+ * Copyright (c) 2012-2013,2015,2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -320,6 +320,11 @@
*/
void finishTranslation(WholeTranslationState *state);
+ /** hardware transactional memory **/
+ Fault initiateHtmCmd(Request::Flags flags) override;
+
+ void htmSendAbortSignal(HtmFailureFaultCause) override;
+
private:
EventFunctionWrapper fetchEvent;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30322
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iff95eb97603b4cb9629c04382a824b02594ee5c7
Gerrit-Change-Number: 30322
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Timothy Hayes <timothy.ha...@arm.com>
Gerrit-MessageType: newchange
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