Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30554 )
Change subject: cpu-o3: Avoid passing ReExec 'faults' on CPU tracing
interface
......................................................................
cpu-o3: Avoid passing ReExec 'faults' on CPU tracing interface
The O3 model uses ReExec faults to flush the pipeline and restart
after a memory ordering violation, e.g. due to an incoming snoop.
These, just like branch mispredict flushes, are not architectural
faults but micro-architectural events, and should therefore not
show up on the instruction tracing interface.
This adds a check on faulting instructions in commit, to verify
if the instruction faulted due to ReExec, to avoid tracing it.
Change-Id: I1d3eaffb0ff22411e0e16a69ef07961924c88c10
---
M src/cpu/o3/commit_impl.hh
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 4f467e9..49b40e3 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1259,7 +1259,11 @@
"[tid:%i] [sn:%llu] Committing instruction with fault\n",
tid, head_inst->seqNum);
if (head_inst->traceData) {
- if (DTRACE(ExecFaulting)) {
+ // We ignore ReExecution "faults" here as they are not real
+ // (architectural) faults but signal flush/replays.
+ if (DTRACE(ExecFaulting)
+ && dynamic_cast<ReExec*>(inst_fault.get()) == nullptr) {
+
head_inst->traceData->setFaulting(true);
head_inst->traceData->setFetchSeq(head_inst->seqNum);
head_inst->traceData->setCPSeq(thread[tid]->numOp);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1d3eaffb0ff22411e0e16a69ef07961924c88c10
Gerrit-Change-Number: 30554
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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