[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix routeToHyp conditions for Excp Type

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30620 )

Change subject: arch-arm: Fix routeToHyp conditions for Excp Type
......................................................................

arch-arm: Fix routeToHyp conditions for Excp Type

Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
---
M src/arch/arm/faults.cc
1 file changed, 8 insertions(+), 43 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ba8369a..00a70ed 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -857,17 +857,8 @@
 bool
 SupervisorCall::routeToHyp(ThreadContext *tc) const
 {
-    bool toHyp;
-
-    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-    // if in Hyp mode then stay in Hyp mode
-    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
-    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-    return toHyp;
+    return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
 }

 ExceptionClass
@@ -999,15 +990,8 @@
 bool
 SupervisorTrap::routeToHyp(ThreadContext *tc) const
 {
-    bool toHyp = false;
-
-    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-    return toHyp;
+    return hcr.tge && (currEL(tc) <= EL1) && EL2Enabled(tc);
 }

 uint32_t
@@ -1289,6 +1273,7 @@

     // if in Hyp mode then stay in Hyp mode
     toHyp = scr.ns && (currEL(tc) == EL2);
+    toHyp |= (currEL(tc) <= EL1) && hcr.tge;
     // otherwise, check whether to take to Hyp mode through Hyp Trap vector
     toHyp |= (stage2 ||
               ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
@@ -1350,6 +1335,7 @@

     // if in Hyp mode then stay in Hyp mode
     toHyp = scr.ns && (currEL(tc) == EL2);
+    toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
     // otherwise, check whether to take to Hyp mode through Hyp Trap vector
     toHyp |= (stage2 ||
               ((currEL(tc) != EL2) &&
@@ -1450,15 +1436,8 @@
 bool
 Interrupt::routeToHyp(ThreadContext *tc) const
 {
-    bool toHyp;
-
-    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-    // Determine whether IRQs are routed to Hyp mode.
-    toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
-            (cpsr.mode == MODE_HYP);
-    return toHyp;
+    return EL2Enabled(tc) &&currEL(tc) <= EL1 && (hcr.tge==1 || hcr.fmo);
 }

 bool
@@ -1489,15 +1468,8 @@
 bool
 FastInterrupt::routeToHyp(ThreadContext *tc) const
 {
-    bool toHyp;
-
-    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
-    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-    // Determine whether IRQs are routed to Hyp mode.
-    toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
-            (cpsr.mode == MODE_HYP);
-    return toHyp;
+    return EL2Enabled(tc) &&currEL(tc) <= EL1 && (hcr.tge == 1 || hcr.fmo);
 }

 bool
@@ -1537,15 +1509,8 @@
 bool
 PCAlignmentFault::routeToHyp(ThreadContext *tc) const
 {
-    bool toHyp = false;
-
-    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-    return toHyp;
+    return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
 }

 SPAlignmentFault::SPAlignmentFault()
@@ -1556,7 +1521,7 @@
 {
     assert(from64);
     HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-    return EL2Enabled(tc) && hcr.tge==1;
+    return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
 }

 SystemError::SystemError()

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
Gerrit-Change-Number: 30620
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero <jordi.vaqu...@metempsy.com>
Gerrit-MessageType: newchange
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