Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31054 )

Change subject: dev-arm: Move GICv2 intConfig for consistency
......................................................................

dev-arm: Move GICv2 intConfig for consistency

Every other helper is placed below the respective array storage

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31054
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 4ef1517..3213379 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -72,7 +72,7 @@
       enabled(false), haveGem5Extensions(p->gem5_extensions),
       itLines(p->it_lines),
       intEnabled {}, pendingInt {}, activeInt {},
-      intPriority {}, cpuTarget {}, intConfig {},
+      intPriority {}, intConfig {}, cpuTarget {},
       cpuSgiPending {}, cpuSgiActive {},
       cpuSgiPendingExt {}, cpuSgiActiveExt {},
       cpuPpiPending {}, cpuPpiActive {},
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 600f9af..40a9553 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -281,6 +281,10 @@
         }
     }

+    /** 2 bit per interrupt signaling if it's level or edge sensitive
+     * and if it is 1:N or N:N */
+    uint32_t intConfig[INT_BITS_MAX*2];
+
     /** GICD_ICFGRn
      * get 2 bit config associated to an interrupt.
      */
@@ -319,10 +323,6 @@
         }
     }

-    /** 2 bit per interrupt signaling if it's level or edge sensitive
-     * and if it is 1:N or N:N */
-    uint32_t intConfig[INT_BITS_MAX*2];
-
     bool isLevelSensitive(ContextID ctx, uint32_t ix) {
         if (ix == SPURIOUS_INT) {
             return false;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31054
To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3
Gerrit-Change-Number: 31054
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

Reply via email to