Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31867 )
Change subject: misc: Rename source code inclusion of DRAMSim3
......................................................................
misc: Rename source code inclusion of DRAMSim3
Change-Id: I99f5e665cb06dc180632f176e069503c381446aa
---
M .gitignore
M configs/common/MemConfig.py
M ext/dramsim3/SConscript
R src/mem/DRAMsim3.py
M src/mem/SConscript
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/dramsim3_wrapper.cc
M src/mem/dramsim3_wrapper.hh
9 files changed, 101 insertions(+), 101 deletions(-)
diff --git a/.gitignore b/.gitignore
index 679c9f7..00a8756 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,7 +10,7 @@
m5out
/src/doxygen/html
/ext/dramsim2/DRAMSim2
-/ext/dramsim3/DRAMSim3
+/ext/dramsim3/DRAMsim3
/ext/mcpat/regression/*/*.out
/util/m5/*.o
/util/m5/*.a
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index ae04607..4831c86 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -89,7 +89,7 @@
return _mem_classes.keys()
def dramsim3_size_mb(ini_file):
- """Parsing ini file for DRAMSim3 so that the system knows mem size"""
+ """Parsing ini file for DRAMsim3 so that the system knows mem size"""
assert(os.path.exists(ini_file))
import ConfigParser
config = ConfigParser.ConfigParser()
@@ -179,12 +179,12 @@
opt_xor_low_bit = getattr(options, "xor_low_bit", 0)
opt_dramsim3_ini = getattr(options, 'dramsim3_ini', None)
- if opt_mem_type == "DRAMSim3":
+ if opt_mem_type == "DRAMsim3":
ini_file = ''
if opt_dramsim3_ini:
ini_file = opt_dramsim3_ini
else:
- ini_file = m5.objects.DRAMSim3.config_file
+ ini_file = m5.objects.DRAMsim3.config_file
mem_size = dramsim3_size_mb(ini_file)
mem_size_str = str(mem_size) + "MB"
options.mem_size = mem_size_str
@@ -241,9 +241,9 @@
# address mapping in the case of a DRAM
for r in system.mem_ranges:
for i in xrange(nbr_mem_ctrls):
- # We need to do a couple of things differently for DRAMSim3
+ # We need to do a couple of things differently for DRAMsim3
# use same outdir as gem5, and use its own address mapping
- if opt_mem_type == 'DRAMSim3':
+ if opt_mem_type == 'DRAMsim3':
mem_ctrl = cls()
if opt_dramsim3_ini:
mem_ctrl.config_file = opt_dramsim3_ini
diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
index 13b13fb..3fcff46 100644
--- a/ext/dramsim3/SConscript
+++ b/ext/dramsim3/SConscript
@@ -45,7 +45,7 @@
# See if we got a cloned DRAMSim3 repo as a subdirectory and set the
# HAVE_DRAMSIM flag accordingly
-if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMSim3'):
+if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMsim3'):
main['HAVE_DRAMSIM3'] = False
Return()
@@ -53,7 +53,7 @@
main['HAVE_DRAMSIM3'] = True
-dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3/')
+dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMsim3/')
if thermal:
superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')
diff --git a/src/mem/DRAMSim3.py b/src/mem/DRAMsim3.py
similarity index 93%
rename from src/mem/DRAMSim3.py
rename to src/mem/DRAMsim3.py
index c8f3efe..3b00192 100644
--- a/src/mem/DRAMSim3.py
+++ b/src/mem/DRAMsim3.py
@@ -39,15 +39,15 @@
from AbstractMemory import *
# A wrapper for DRAMSim2 multi-channel memory controller
-class DRAMSim3(AbstractMemory):
- type = 'DRAMSim3'
+class DRAMsim3(AbstractMemory):
+ type = 'DRAMsim3'
cxx_header = "mem/dramsim3.hh"
# A single port for now
port = SlavePort("Slave port")
- config_file = Param.String("ext/dramsim3/DRAMSim3/configs/"
+ config_file = Param.String("ext/dramsim3/DRAMsim3/configs/"
"DDR4_8Gb_x8_2400.ini",
"One configuration file")
- file_path = Param.String("ext/dramsim3/DRAMSim3/",
+ file_path = Param.String("ext/dramsim3/DRAMsim3/",
"Directory to prepend to file names")
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 467b188..8dcb63a 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -91,7 +91,7 @@
Source('dramsim2.cc')
if env['HAVE_DRAMSIM3']:
- SimObject('DRAMSim3.py')
+ SimObject('DRAMsim3.py')
Source('dramsim3_wrapper.cc')
Source('dramsim3.cc')
@@ -119,7 +119,7 @@
DebugFlag('PacketQueue')
DebugFlag('StackDist')
DebugFlag("DRAMSim2")
-DebugFlag("DRAMSim3")
+DebugFlag("DRAMsim3")
DebugFlag('HMCController')
DebugFlag('SerialLink')
DebugFlag('TokenPort')
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index ef275b0..c739609 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -41,16 +41,16 @@
#include "base/callback.hh"
#include "base/trace.hh"
-#include "debug/DRAMSim3.hh"
+#include "debug/DRAMsim3.hh"
#include "debug/Drain.hh"
#include "sim/system.hh"
-DRAMSim3::DRAMSim3(const Params* p) :
+DRAMsim3::DRAMsim3(const Params* p) :
AbstractMemory(p),
port(name() + ".port", *this),
- read_cb(std::bind(&DRAMSim3::readComplete,
+ read_cb(std::bind(&DRAMsim3::readComplete,
this, 0, std::placeholders::_1)),
- write_cb(std::bind(&DRAMSim3::writeComplete,
+ write_cb(std::bind(&DRAMsim3::writeComplete,
this, 0, std::placeholders::_1)),
wrapper(p->config_file, p->file_path, read_cb, write_cb),
retryReq(false), retryResp(false), startTick(0),
@@ -58,35 +58,35 @@
sendResponseEvent([this]{ sendResponse(); }, name()),
tickEvent([this]{ tick(); }, name())
{
- DPRINTF(DRAMSim3,
- "Instantiated DRAMSim3 with clock %d ns and queue size %d\n",
+ DPRINTF(DRAMsim3,
+ "Instantiated DRAMsim3 with clock %d ns and queue size %d\n",
wrapper.clockPeriod(), wrapper.queueSize());
// Register a callback to compensate for the destructor not
- // being called. The callback prints the DRAMSim3 stats.
- Callback* cb = new MakeCallback<DRAMSim3Wrapper,
- &DRAMSim3Wrapper::printStats>(wrapper);
+ // being called. The callback prints the DRAMsim3 stats.
+ Callback* cb = new MakeCallback<DRAMsim3Wrapper,
+ &DRAMsim3Wrapper::printStats>(wrapper);
registerExitCallback(cb);
}
void
-DRAMSim3::init()
+DRAMsim3::init()
{
AbstractMemory::init();
if (!port.isConnected()) {
- fatal("DRAMSim3 %s is unconnected!\n", name());
+ fatal("DRAMsim3 %s is unconnected!\n", name());
} else {
port.sendRangeChange();
}
if (system()->cacheLineSize() != wrapper.burstSize())
- fatal("DRAMSim3 burst size %d does not match cache line size %d\n",
+ fatal("DRAMsim3 burst size %d does not match cache line size %d\n",
wrapper.burstSize(), system()->cacheLineSize());
}
void
-DRAMSim3::startup()
+DRAMsim3::startup()
{
startTick = curTick();
@@ -95,23 +95,23 @@
}
void
-DRAMSim3::resetStats() {
+DRAMsim3::resetStats() {
wrapper.resetStats();
}
void
-DRAMSim3::sendResponse()
+DRAMsim3::sendResponse()
{
assert(!retryResp);
assert(!responseQueue.empty());
- DPRINTF(DRAMSim3, "Attempting to send response\n");
+ DPRINTF(DRAMsim3, "Attempting to send response\n");
bool success = port.sendTimingResp(responseQueue.front());
if (success) {
responseQueue.pop_front();
- DPRINTF(DRAMSim3, "Have %d read, %d write, %d responses
outstanding\n",
+ DPRINTF(DRAMsim3, "Have %d read, %d write, %d responses
outstanding\n",
nbrOutstandingReads, nbrOutstandingWrites,
responseQueue.size());
@@ -123,20 +123,20 @@
} else {
retryResp = true;
- DPRINTF(DRAMSim3, "Waiting for response retry\n");
+ DPRINTF(DRAMsim3, "Waiting for response retry\n");
assert(!sendResponseEvent.scheduled());
}
}
unsigned int
-DRAMSim3::nbrOutstanding() const
+DRAMsim3::nbrOutstanding() const
{
return nbrOutstandingReads + nbrOutstandingWrites +
responseQueue.size();
}
void
-DRAMSim3::tick()
+DRAMsim3::tick()
{
// Only tick when it's timing mode
if (system()->isTimingMode()) {
@@ -154,7 +154,7 @@
}
Tick
-DRAMSim3::recvAtomic(PacketPtr pkt)
+DRAMsim3::recvAtomic(PacketPtr pkt)
{
access(pkt);
@@ -163,7 +163,7 @@
}
void
-DRAMSim3::recvFunctional(PacketPtr pkt)
+DRAMsim3::recvFunctional(PacketPtr pkt)
{
pkt->pushLabel(name());
@@ -177,7 +177,7 @@
}
bool
-DRAMSim3::recvTimingReq(PacketPtr pkt)
+DRAMsim3::recvTimingReq(PacketPtr pkt)
{
// if a cache is responding, sink the packet without further action
if (pkt->cacheResponding()) {
@@ -225,7 +225,7 @@
// and there isn't
assert(wrapper.canAccept(pkt->getAddr(), pkt->isWrite()));
- DPRINTF(DRAMSim3, "Enqueueing address %lld\n", pkt->getAddr());
+ DPRINTF(DRAMsim3, "Enqueueing address %lld\n", pkt->getAddr());
// @todo what about the granularity here, implicit assumption that
// a transaction matches the burst size of the memory (which we
@@ -240,9 +240,9 @@
}
void
-DRAMSim3::recvRespRetry()
+DRAMsim3::recvRespRetry()
{
- DPRINTF(DRAMSim3, "Retrying\n");
+ DPRINTF(DRAMsim3, "Retrying\n");
assert(retryResp);
retryResp = false;
@@ -250,9 +250,9 @@
}
void
-DRAMSim3::accessAndRespond(PacketPtr pkt)
+DRAMsim3::accessAndRespond(PacketPtr pkt)
{
- DPRINTF(DRAMSim3, "Access for address %lld\n", pkt->getAddr());
+ DPRINTF(DRAMsim3, "Access for address %lld\n", pkt->getAddr());
bool needsResponse = pkt->needsResponse();
@@ -270,7 +270,7 @@
// Reset the timings of the packet
pkt->headerDelay = pkt->payloadDelay = 0;
- DPRINTF(DRAMSim3, "Queuing response for address %lld\n",
+ DPRINTF(DRAMsim3, "Queuing response for address %lld\n",
pkt->getAddr());
// queue it to be sent back
@@ -286,10 +286,10 @@
}
}
-void DRAMSim3::readComplete(unsigned id, uint64_t addr)
+void DRAMsim3::readComplete(unsigned id, uint64_t addr)
{
- DPRINTF(DRAMSim3, "Read to address %lld complete\n", addr);
+ DPRINTF(DRAMsim3, "Read to address %lld complete\n", addr);
// get the outstanding reads for the address in question
auto p = outstandingReads.find(addr);
@@ -312,10 +312,10 @@
accessAndRespond(pkt);
}
-void DRAMSim3::writeComplete(unsigned id, uint64_t addr)
+void DRAMsim3::writeComplete(unsigned id, uint64_t addr)
{
- DPRINTF(DRAMSim3, "Write to address %lld complete\n", addr);
+ DPRINTF(DRAMsim3, "Write to address %lld complete\n", addr);
// get the outstanding reads for the address in question
auto p = outstandingWrites.find(addr);
@@ -335,7 +335,7 @@
}
BaseSlavePort&
-DRAMSim3::getSlavePort(const std::string &if_name, PortID idx)
+DRAMsim3::getSlavePort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
return MemObject::getSlavePort(if_name, idx);
@@ -345,20 +345,20 @@
}
DrainState
-DRAMSim3::drain()
+DRAMsim3::drain()
{
// check our outstanding reads and writes and if any they need to
// drain
return nbrOutstanding() != 0 ? DrainState::Draining :
DrainState::Drained;
}
-DRAMSim3::MemoryPort::MemoryPort(const std::string& _name,
- DRAMSim3& _memory)
+DRAMsim3::MemoryPort::MemoryPort(const std::string& _name,
+ DRAMsim3& _memory)
: SlavePort(_name, &_memory), memory(_memory)
{ }
AddrRangeList
-DRAMSim3::MemoryPort::getAddrRanges() const
+DRAMsim3::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
ranges.push_back(memory.getAddrRange());
@@ -366,32 +366,32 @@
}
Tick
-DRAMSim3::MemoryPort::recvAtomic(PacketPtr pkt)
+DRAMsim3::MemoryPort::recvAtomic(PacketPtr pkt)
{
return memory.recvAtomic(pkt);
}
void
-DRAMSim3::MemoryPort::recvFunctional(PacketPtr pkt)
+DRAMsim3::MemoryPort::recvFunctional(PacketPtr pkt)
{
memory.recvFunctional(pkt);
}
bool
-DRAMSim3::MemoryPort::recvTimingReq(PacketPtr pkt)
+DRAMsim3::MemoryPort::recvTimingReq(PacketPtr pkt)
{
// pass it to the memory controller
return memory.recvTimingReq(pkt);
}
void
-DRAMSim3::MemoryPort::recvRespRetry()
+DRAMsim3::MemoryPort::recvRespRetry()
{
memory.recvRespRetry();
}
-DRAMSim3*
-DRAMSim3Params::create()
+DRAMsim3*
+DRAMsim3Params::create()
{
- return new DRAMSim3(this);
+ return new DRAMsim3(this);
}
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index 7a1a813..e75fff4 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -39,7 +39,7 @@
/**
* @file
- * DRAMSim3
+ * DRAMsim3
*/
#ifndef __MEM_DRAMSIM3_HH__
#define __MEM_DRAMSIM3_HH__
@@ -51,9 +51,9 @@
#include "mem/abstract_mem.hh"
#include "mem/dramsim3_wrapper.hh"
#include "mem/qport.hh"
-#include "params/DRAMSim3.hh"
+#include "params/DRAMsim3.hh"
-class DRAMSim3 : public AbstractMemory
+class DRAMsim3 : public AbstractMemory
{
private:
@@ -67,11 +67,11 @@
private:
- DRAMSim3& memory;
+ DRAMsim3& memory;
public:
- MemoryPort(const std::string& _name, DRAMSim3& _memory);
+ MemoryPort(const std::string& _name, DRAMsim3& _memory);
protected:
@@ -96,9 +96,9 @@
std::function<void(uint64_t)> write_cb;
/**
- * The actual DRAMSim3 wrapper
+ * The actual DRAMsim3 wrapper
*/
- DRAMSim3Wrapper wrapper;
+ DRAMsim3Wrapper wrapper;
/**
* Is the connected port waiting for a retry from us
@@ -126,7 +126,7 @@
/**
* Count the number of outstanding transactions so that we can
- * block any further requests until there is space in DRAMSim3 and
+ * block any further requests until there is space in DRAMsim3 and
* the sending queue we need to buffer the response packets.
*/
unsigned int nbrOutstandingReads;
@@ -134,7 +134,7 @@
/**
* Queue to hold response packets until we can send them
- * back. This is needed as DRAMSim3 unconditionally passes
+ * back. This is needed as DRAMsim3 unconditionally passes
* responses back without any flow control.
*/
std::deque<PacketPtr> responseQueue;
@@ -176,15 +176,15 @@
public:
- typedef DRAMSim3Params Params;
- DRAMSim3(const Params *p);
+ typedef DRAMsim3Params Params;
+ DRAMsim3(const Params *p);
/**
* Read completion callback.
*
* @param id Channel id of the responder
* @param addr Address of the request
- * @param cycle Internal cycle count of DRAMSim3
+ * @param cycle Internal cycle count of DRAMsim3
*/
void readComplete(unsigned id, uint64_t addr);
@@ -193,7 +193,7 @@
*
* @param id Channel id of the responder
* @param addr Address of the request
- * @param cycle Internal cycle count of DRAMSim3
+ * @param cycle Internal cycle count of DRAMsim3
*/
void writeComplete(unsigned id, uint64_t addr);
diff --git a/src/mem/dramsim3_wrapper.cc b/src/mem/dramsim3_wrapper.cc
index fd437c3..0cfa155 100644
--- a/src/mem/dramsim3_wrapper.cc
+++ b/src/mem/dramsim3_wrapper.cc
@@ -41,7 +41,7 @@
/**
* When building the debug binary, we need to undo the command-line
- * definition of DEBUG not to clash with DRAMSim3 print macros that
+ * definition of DEBUG not to clash with DRAMsim3 print macros that
* are included for no obvious reason.
*/
#ifdef DEBUG
@@ -52,11 +52,11 @@
#include <fstream>
-#include "DRAMSim3/src/dramsim3.h"
+#include "DRAMsim3/src/dramsim3.h"
#include "base/compiler.hh"
#include "base/logging.hh"
-DRAMSim3Wrapper::DRAMSim3Wrapper(const std::string& config_file,
+DRAMsim3Wrapper::DRAMsim3Wrapper(const std::string& config_file,
const std::string& working_dir,
std::function<void(uint64_t)> read_cb,
std::function<void(uint64_t)> write_cb) :
@@ -64,19 +64,19 @@
read_cb, write_cb)),
_clockPeriod(0.0), _queueSize(0), _burstSize(0)
{
- // there is no way of getting DRAMSim3 to tell us what frequency
+ // there is no way of getting DRAMsim3 to tell us what frequency
// it is assuming, so we have to extract it ourselves
_clockPeriod = dramsim->GetTCK();
if (!_clockPeriod)
- fatal("DRAMSim3 wrapper failed to get clock\n");
+ fatal("DRAMsim3 wrapper failed to get clock\n");
- // we also need to know what transaction queue size DRAMSim3 is
+ // we also need to know what transaction queue size DRAMsim3 is
// using so we can stall when responses are blocked
_queueSize = dramsim->GetQueueSize();
if (!_queueSize)
- fatal("DRAMSim3 wrapper failed to get queue size\n");
+ fatal("DRAMsim3 wrapper failed to get queue size\n");
// finally, get the data bus bits and burst length so we can add a
@@ -85,69 +85,69 @@
unsigned int burstLength = dramsim->GetBurstLength();
if (!dataBusBits || !burstLength)
- fatal("DRAMSim3 wrapper failed to get burst size\n");
+ fatal("DRAMsim3 wrapper failed to get burst size\n");
_burstSize = dataBusBits * burstLength / 8;
}
-DRAMSim3Wrapper::~DRAMSim3Wrapper()
+DRAMsim3Wrapper::~DRAMsim3Wrapper()
{
delete dramsim;
}
void
-DRAMSim3Wrapper::printStats()
+DRAMsim3Wrapper::printStats()
{
dramsim->PrintStats();
}
void
-DRAMSim3Wrapper::resetStats()
+DRAMsim3Wrapper::resetStats()
{
dramsim->ResetStats();
}
void
-DRAMSim3Wrapper::setCallbacks(std::function<void(uint64_t)> read_complete,
+DRAMsim3Wrapper::setCallbacks(std::function<void(uint64_t)> read_complete,
std::function<void(uint64_t)> write_complete)
{
dramsim->RegisterCallbacks(read_complete, write_complete);
}
bool
-DRAMSim3Wrapper::canAccept(uint64_t addr, bool is_write) const
+DRAMsim3Wrapper::canAccept(uint64_t addr, bool is_write) const
{
return dramsim->WillAcceptTransaction(addr, is_write);
}
void
-DRAMSim3Wrapper::enqueue(uint64_t addr, bool is_write)
+DRAMsim3Wrapper::enqueue(uint64_t addr, bool is_write)
{
bool success M5_VAR_USED = dramsim->AddTransaction(addr, is_write);
assert(success);
}
double
-DRAMSim3Wrapper::clockPeriod() const
+DRAMsim3Wrapper::clockPeriod() const
{
return _clockPeriod;
}
unsigned int
-DRAMSim3Wrapper::queueSize() const
+DRAMsim3Wrapper::queueSize() const
{
return _queueSize;
}
unsigned int
-DRAMSim3Wrapper::burstSize() const
+DRAMsim3Wrapper::burstSize() const
{
return _burstSize;
}
void
-DRAMSim3Wrapper::tick()
+DRAMsim3Wrapper::tick()
{
dramsim->ClockTick();
}
diff --git a/src/mem/dramsim3_wrapper.hh b/src/mem/dramsim3_wrapper.hh
index 8053101..ada6152 100644
--- a/src/mem/dramsim3_wrapper.hh
+++ b/src/mem/dramsim3_wrapper.hh
@@ -39,7 +39,7 @@
/**
* @file
- * DRAMSim3Wrapper declaration
+ * DRAMsim3Wrapper declaration
*/
#ifndef __MEM_DRAMSIM3_WRAPPER_HH__
@@ -58,14 +58,14 @@
}
/**
- * Wrapper class to avoid having DRAMSim3 names like ClockDomain etc
- * clashing with the normal gem5 world. Many of the DRAMSim3 headers
+ * Wrapper class to avoid having DRAMsim3 names like ClockDomain etc
+ * clashing with the normal gem5 world. Many of the DRAMsim3 headers
* do not make use of namespaces, and quite a few also open up
* std. The only thing that needs to be exposed externally are the
* callbacks. This wrapper effectively avoids clashes by not including
* any of the conventional gem5 headers (e.g. Packet or SimObject).
*/
-class DRAMSim3Wrapper
+class DRAMsim3Wrapper
{
private:
@@ -85,17 +85,17 @@
public:
/**
- * Create an instance of the DRAMSim3 multi-channel memory
+ * Create an instance of the DRAMsim3 multi-channel memory
* controller using a specific config and system description.
*
* @param config_file Memory config file
* @param working_dir Path pre-pended to config files
*/
- DRAMSim3Wrapper(const std::string& config_file,
+ DRAMsim3Wrapper(const std::string& config_file,
const std::string& working_dir,
std::function<void(uint64_t)> read_cb,
std::function<void(uint64_t)> write_cb);
- ~DRAMSim3Wrapper();
+ ~DRAMsim3Wrapper();
/**
* Print the stats gathered in DRAMsim3.
@@ -126,12 +126,12 @@
/**
* Enqueue a packet. This assumes that canAccept has returned true.
*
- * @param pkt Packet to turn into a DRAMSim3 transaction
+ * @param pkt Packet to turn into a DRAMsim3 transaction
*/
void enqueue(uint64_t addr, bool is_write);
/**
- * Get the internal clock period used by DRAMSim3, specified in
+ * Get the internal clock period used by DRAMsim3, specified in
* ns.
*
* @return The clock period of the DRAM interface in ns
@@ -139,14 +139,14 @@
double clockPeriod() const;
/**
- * Get the transaction queue size used by DRAMSim3.
+ * Get the transaction queue size used by DRAMsim3.
*
* @return The queue size counted in number of transactions
*/
unsigned int queueSize() const;
/**
- * Get the burst size in bytes used by DRAMSim3.
+ * Get the burst size in bytes used by DRAMsim3.
*
* @return The burst size in bytes (data width * burst length)
*/
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I99f5e665cb06dc180632f176e069503c381446aa
Gerrit-Change-Number: 31867
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-MessageType: newchange
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