Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31939 )
Change subject: dev-arm: Make the Sp805 use the new ArmInterruptPin::active
......................................................................
dev-arm: Make the Sp805 use the new ArmInterruptPin::active
Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31939
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/dev/arm/watchdog_sp805.cc
M src/dev/arm/watchdog_sp805.hh
2 files changed, 3 insertions(+), 11 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/watchdog_sp805.cc b/src/dev/arm/watchdog_sp805.cc
index bed6258..3fd7006 100644
--- a/src/dev/arm/watchdog_sp805.cc
+++ b/src/dev/arm/watchdog_sp805.cc
@@ -49,7 +49,6 @@
persistedValue(timeoutInterval),
enabled(false),
resetEnabled(false),
- intRaised(false),
writeAccessEnabled(true),
integrationTestEnabled(false),
timeoutEvent([this] { timeoutExpired(); }, name())
@@ -78,10 +77,10 @@
warn("Sp805::read: WO reg (0x%x) [WDOGINTCLR]\n", addr);
break;
case WDOGRIS:
- resp = intRaised;
+ resp = interrupt->active();
break;
case WDOGMIS:
- resp = intRaised & enabled;
+ resp = interrupt->active() && enabled;
break;
case WDOGLOCK:
resp = writeAccessEnabled;
@@ -210,11 +209,10 @@
{
// If the previously sent interrupt has not been served,
// assert system reset if enabled
- if (intRaised & enabled) {
+ if (interrupt->active() && enabled) {
if (resetEnabled)
warn("Watchdog timed out, system reset asserted\n");
} else {
- intRaised = true;
interrupt->raise();
}
}
@@ -222,7 +220,6 @@
void
Sp805::clearInt()
{
- intRaised = false;
interrupt->clear();
}
@@ -234,7 +231,6 @@
SERIALIZE_SCALAR(persistedValue);
SERIALIZE_SCALAR(enabled);
SERIALIZE_SCALAR(resetEnabled);
- SERIALIZE_SCALAR(intRaised);
SERIALIZE_SCALAR(writeAccessEnabled);
SERIALIZE_SCALAR(integrationTestEnabled);
@@ -252,7 +248,6 @@
UNSERIALIZE_SCALAR(persistedValue);
UNSERIALIZE_SCALAR(enabled);
UNSERIALIZE_SCALAR(resetEnabled);
- UNSERIALIZE_SCALAR(intRaised);
UNSERIALIZE_SCALAR(writeAccessEnabled);
UNSERIALIZE_SCALAR(integrationTestEnabled);
diff --git a/src/dev/arm/watchdog_sp805.hh b/src/dev/arm/watchdog_sp805.hh
index c2e99cd..4d9094d 100644
--- a/src/dev/arm/watchdog_sp805.hh
+++ b/src/dev/arm/watchdog_sp805.hh
@@ -93,9 +93,6 @@
/** Indicates if reset behaviour is enabled when counter reaches 0 */
bool resetEnabled;
- /** Indicates if an interrupt has been raised by the counter reaching
0 */
- bool intRaised;
-
/** Indicates if write access to registers is enabled */
bool writeAccessEnabled;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Gerrit-Change-Number: 31939
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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