Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32236 )
Change subject: arch-gcn3: make read2st64_b32 write proper registers
......................................................................
arch-gcn3: make read2st64_b32 write proper registers
Per the GCN3 ISA, read2st64_b32 writes to consecutive registers
Change-Id: Ibc1672584a72cf7de12e06068a03fe304b34dce2
---
M src/arch/gcn3/insts/instructions.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index 6e81e2c..955d801 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -32206,7 +32206,7 @@
Inst_DS__DS_READ2ST64_B32::completeAcc(GPUDynInstPtr gpuDynInst)
{
VecOperandU32 vdst0(gpuDynInst, extData.VDST);
- VecOperandU32 vdst1(gpuDynInst, extData.VDST + 2);
+ VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc1672584a72cf7de12e06068a03fe304b34dce2
Gerrit-Change-Number: 32236
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty <kyleroarty1...@gmail.com>
Gerrit-MessageType: newchange
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