Hello Emily Brickey,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/32313
to review the following change.
Change subject: gpu-compute: update port terminology
......................................................................
gpu-compute: update port terminology
Change-Id: I3121c4afb1e137aebe09c1d694e9484844d02b9b
---
M src/gpu-compute/GPU.py
M src/gpu-compute/LdsState.py
M src/gpu-compute/X86GPUTLB.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/lds_state.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
9 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index 7408bf9..f6f29de 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -161,10 +161,10 @@
memory_port = VectorMasterPort("Port to the memory system")
translation_port = VectorMasterPort('Port to the TLB hierarchy')
- sqc_port = MasterPort("Port to the SQC (I-cache")
- sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)")
- scalar_port = MasterPort("Port to the scalar data cache")
- scalar_tlb_port = MasterPort("Port to the TLB for the scalar data
cache")
+ sqc_port = RequestPort("Port to the SQC (I-cache")
+ sqc_tlb_port = RequestPort("Port to the TLB for the SQC (I-cache)")
+ scalar_port = RequestPort("Port to the scalar data cache")
+ scalar_tlb_port = RequestPort("Port to the TLB for the scalar data
cache")
perLaneTLB = Param.Bool(False, "enable per-lane TLB")
prefetch_depth = Param.Int(0, "Number of prefetches triggered at a
time"\
"(0 turns off prefetching)")
@@ -192,7 +192,7 @@
max_cu_tokens = Param.Int(4, "Maximum number of tokens, i.e., the
number"\
" of instructions that can be sent to
coalescer")
ldsBus = Bridge() # the bridge between the CU and its LDS
- ldsPort = MasterPort("The port that goes to the LDS")
+ ldsPort = RequestPort("The port that goes to the LDS")
localDataStore = Param.LdsState("the LDS for this CU")
vector_register_file = VectorParam.VectorRegisterFile("Vector
register "\
diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py
index 2cf8c3a..6bd0a7e 100644
--- a/src/gpu-compute/LdsState.py
+++ b/src/gpu-compute/LdsState.py
@@ -44,4 +44,4 @@
bankConflictPenalty = Param.Int(1, 'penalty per LDS bank conflict
when '\
'accessing data')
banks = Param.Int(32, 'Number of LDS banks')
- cuPort = SlavePort("port that goes to the compute unit")
+ cuPort = ResponsePort("port that goes to the compute unit")
diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index 701743d..bd22bee 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -40,7 +40,7 @@
class X86PagetableWalker(SimObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
- port = SlavePort("Port for the hardware table walker")
+ port = ResponsePort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86GPUTLB(ClockedObject):
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index 067c254..849fe35 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -2593,7 +2593,7 @@
computeUnit->cu_id, gpuDynInst->simdId,
gpuDynInst->wfSlotId);
return false;
- } else if (!MasterPort::sendTimingReq(pkt)) {
+ } else if (!RequestPort::sendTimingReq(pkt)) {
// need to stall the LDS port until a recvReqRetry() is received
// this indicates that there is more space
stallPort();
@@ -2637,7 +2637,7 @@
DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id);
- if (!MasterPort::sendTimingReq(packet)) {
+ if (!RequestPort::sendTimingReq(packet)) {
// Stall port
stallPort();
DPRINTF(GPUPort, ": LDS send failed again\n");
diff --git a/src/gpu-compute/compute_unit.hh
b/src/gpu-compute/compute_unit.hh
index 22960c0..a3d308e 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -671,11 +671,11 @@
GMTokenPort gmTokenPort;
/** Data access Port **/
- class DataPort : public MasterPort
+ class DataPort : public RequestPort
{
public:
DataPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
- : MasterPort(_name, _cu), computeUnit(_cu),
+ : RequestPort(_name, _cu), computeUnit(_cu),
index(_index) { }
bool snoopRangeSent;
@@ -721,12 +721,12 @@
};
// Scalar data cache access port
- class ScalarDataPort : public MasterPort
+ class ScalarDataPort : public RequestPort
{
public:
ScalarDataPort(const std::string &_name, ComputeUnit *_cu,
PortID _index)
- : MasterPort(_name, _cu, _index), computeUnit(_cu),
index(_index)
+ : RequestPort(_name, _cu, _index), computeUnit(_cu),
index(_index)
{
(void)index;
}
@@ -771,11 +771,11 @@
};
// Instruction cache access port
- class SQCPort : public MasterPort
+ class SQCPort : public RequestPort
{
public:
SQCPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
- : MasterPort(_name, _cu), computeUnit(_cu),
+ : RequestPort(_name, _cu), computeUnit(_cu),
index(_index) { }
bool snoopRangeSent;
@@ -814,11 +814,11 @@
};
/** Data TLB port **/
- class DTLBPort : public MasterPort
+ class DTLBPort : public RequestPort
{
public:
DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
- : MasterPort(_name, _cu), computeUnit(_cu),
+ : RequestPort(_name, _cu), computeUnit(_cu),
index(_index), stalled(false)
{ }
@@ -862,11 +862,11 @@
virtual void recvReqRetry();
};
- class ScalarDTLBPort : public MasterPort
+ class ScalarDTLBPort : public RequestPort
{
public:
ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
- : MasterPort(_name, _cu), computeUnit(_cu), stalled(false)
+ : RequestPort(_name, _cu), computeUnit(_cu), stalled(false)
{
}
@@ -890,11 +890,11 @@
bool stalled;
};
- class ITLBPort : public MasterPort
+ class ITLBPort : public RequestPort
{
public:
ITLBPort(const std::string &_name, ComputeUnit *_cu)
- : MasterPort(_name, _cu), computeUnit(_cu), stalled(false) { }
+ : RequestPort(_name, _cu), computeUnit(_cu), stalled(false) { }
bool isStalled() { return stalled; }
@@ -932,11 +932,11 @@
/**
* the port intended to communicate between the CU and its LDS
*/
- class LDSPort : public MasterPort
+ class LDSPort : public RequestPort
{
public:
LDSPort(const std::string &_name, ComputeUnit *_cu, PortID _id)
- : MasterPort(_name, _cu, _id), computeUnit(_cu)
+ : RequestPort(_name, _cu, _id), computeUnit(_cu)
{
}
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 9186b33..03b22bd 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -236,12 +236,12 @@
void issueTLBLookup(PacketPtr pkt);
// CpuSidePort is the TLB Port closer to the CPU/CU side
- class CpuSidePort : public SlavePort
+ class CpuSidePort : public ResponsePort
{
public:
CpuSidePort(const std::string &_name, GpuTLB * gpu_TLB,
PortID _index)
- : SlavePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) {
}
+ : ResponsePort(_name, gpu_TLB), tlb(gpu_TLB),
index(_index) { }
protected:
GpuTLB *tlb;
@@ -263,12 +263,12 @@
* Future action item: if we ever do real page walks, then this
port
* should be connected to a RubyPort.
*/
- class MemSidePort : public MasterPort
+ class MemSidePort : public RequestPort
{
public:
MemSidePort(const std::string &_name, GpuTLB * gpu_TLB,
PortID _index)
- : MasterPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index)
{ }
+ : RequestPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index)
{ }
std::deque<PacketPtr> retries;
@@ -325,7 +325,7 @@
// When was the req for this translation issued
uint64_t issueTime;
// Remember where this came from
- std::vector<SlavePort*>ports;
+ std::vector<ResponsePort*>ports;
// keep track of #uncoalesced reqs per packet per TLB level;
// reqCnt per level >= reqCnt higher level
diff --git a/src/gpu-compute/lds_state.hh b/src/gpu-compute/lds_state.hh
index d793f0f..1caf412 100644
--- a/src/gpu-compute/lds_state.hh
+++ b/src/gpu-compute/lds_state.hh
@@ -157,11 +157,11 @@
/**
* CuSidePort is the LDS Port closer to the CU side
*/
- class CuSidePort: public SlavePort
+ class CuSidePort: public ResponsePort
{
public:
CuSidePort(const std::string &_name, LdsState *_ownerLds) :
- SlavePort(_name, _ownerLds), ownerLds(_ownerLds)
+ ResponsePort(_name, _ownerLds), ownerLds(_ownerLds)
{
}
diff --git a/src/gpu-compute/tlb_coalescer.cc
b/src/gpu-compute/tlb_coalescer.cc
index 51d2e76..b591232 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -198,7 +198,7 @@
sender_state->hitLevel = first_hit_level;
}
- SlavePort *return_port = sender_state->ports.back();
+ ResponsePort *return_port = sender_state->ports.back();
sender_state->ports.pop_back();
// Translation is done - Convert to a response pkt if necessary and
diff --git a/src/gpu-compute/tlb_coalescer.hh
b/src/gpu-compute/tlb_coalescer.hh
index 842237e..aff2515 100644
--- a/src/gpu-compute/tlb_coalescer.hh
+++ b/src/gpu-compute/tlb_coalescer.hh
@@ -137,12 +137,12 @@
void updatePhysAddresses(PacketPtr pkt);
void regStats() override;
- class CpuSidePort : public SlavePort
+ class CpuSidePort : public ResponsePort
{
public:
CpuSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer,
PortID _index)
- : SlavePort(_name, tlb_coalescer), coalescer(tlb_coalescer),
+ : ResponsePort(_name, tlb_coalescer), coalescer(tlb_coalescer),
index(_index) { }
protected:
@@ -165,12 +165,12 @@
virtual AddrRangeList getAddrRanges() const;
};
- class MemSidePort : public MasterPort
+ class MemSidePort : public RequestPort
{
public:
MemSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer,
PortID _index)
- : MasterPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
+ : RequestPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
index(_index) { }
std::deque<PacketPtr> retries;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32313
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3121c4afb1e137aebe09c1d694e9484844d02b9b
Gerrit-Change-Number: 32313
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-Reviewer: Emily Brickey <esbric...@ucdavis.edu>
Gerrit-MessageType: newchange
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