Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32694 )
Change subject: arch-riscv: Fix disassembling of all register instructions
......................................................................
arch-riscv: Fix disassembling of all register instructions
How many Rs to output in disassembling register instructions? It does
not depend on wheather the register index is zero, but on the count
of source registers.
This patch fixes the problem.
Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Signed-off-by: Ian Jiang <ianjiang....@gmail.com>
---
M src/arch/riscv/insts/standard.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index e6c2b67..9a9aa9d 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -48,9 +48,9 @@
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
registerName(_srcRegIdx[0]);
- if (_srcRegIdx[1].index() != 0)
+ if (_numSrcRegs >= 2)
ss << ", " << registerName(_srcRegIdx[1]);
- if (_srcRegIdx[2].index() != 0)
+ if (_numSrcRegs >= 3)
ss << ", " << registerName(_srcRegIdx[2]);
return ss.str();
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32694
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Gerrit-Change-Number: 32694
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang <ianjiang....@gmail.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
