Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32634 )
Change subject: arch-arm: Fix SoftwareStep::debugExceptionReturnSS
......................................................................
arch-arm: Fix SoftwareStep::debugExceptionReturnSS
debugExceptionReturnSS is called on an ERET instruction to
check for software step. The method was not using the
SPSR.width and it was relying on the more generic ELIs32 to
check the execution mode of the destination EL.
This is not only an efficiency problem: the helper might not work
when returning to EL0. In general it is not possible to
understand if EL0 is using AArch32 or AArch64 if the current
EL is not EL0 and EL1 is using AArch64.
This is instead visible by inspecting the spsr.width during the
execution of an ERET instruction
Change-Id: Ibc5a43633d0020139f2c0e372959a3ab4880da6e
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32634
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
3 files changed, 4 insertions(+), 6 deletions(-)
Approvals:
Richard Cooper: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 2281491..e55894c 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1194,7 +1194,7 @@
SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
SoftwareStep *ss = sd->getSstep();
- new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest,
new_cpsr.width);
+ new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest);
return new_cpsr;
}
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index ef6ad63..21ad84c 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -643,7 +643,7 @@
bool
SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
- ExceptionLevel dest, bool aarch32)
+ ExceptionLevel dest)
{
bool SS_bit = false;
bool enabled_src = false;
@@ -652,9 +652,7 @@
bool enabled_dst = false;
bool secure = isSecureBelowEL3(tc) || dest == EL3;
-// CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-// if (cpsr.width) {
- if (ELIs32(tc, dest)) {
+ if (spsr.width) {
enabled_dst = conf->isDebugEnabledForEL32(tc, dest, secure,
spsr.d == 1);
} else {
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 953a2dc..7a96d42 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -210,7 +210,7 @@
{}
bool debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
- ExceptionLevel dest, bool aarch32);
+ ExceptionLevel dest);
bool advanceSS(ThreadContext *tc);
inline void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc5a43633d0020139f2c0e372959a3ab4880da6e
Gerrit-Change-Number: 32634
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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