ZHENGRONG WANG has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32714 )
Change subject: mem-cache: Prefetcher _tlbs should be instance variable.
......................................................................
mem-cache: Prefetcher _tlbs should be instance variable.
The current _tlbs in BasePrefetcher is class variable,
which is shared across all instances. This commit changes
that to instance variable, which is unique to each instance.
This enables multiple prefetchers for multi-cpu, each
with its own TLB.
Change-Id: Ia04d7b5c1582d9b3a5da9f55df02ed76e4c42cf2
---
M src/mem/cache/prefetch/Prefetcher.py
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index f131ccf..233a3bd 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -99,11 +99,14 @@
if len(probeNames) <= 0:
raise TypeError("probeNames must have at least one element")
self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
- _tlbs = []
+
def registerTLB(self, simObj):
if not isinstance(simObj, SimObject):
raise TypeError("argument must be a SimObject type")
- self._tlbs.append(simObj)
+ try:
+ self._tlbs.append(simObj)
+ except AttributeError:
+ self._tlbs = [simObj]
class MultiPrefetcher(BasePrefetcher):
type = 'MultiPrefetcher'
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia04d7b5c1582d9b3a5da9f55df02ed76e4c42cf2
Gerrit-Change-Number: 32714
Gerrit-PatchSet: 1
Gerrit-Owner: ZHENGRONG WANG <sea...@g.ucla.edu>
Gerrit-MessageType: newchange
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