Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33155 )
Change subject: arch-riscv: Fix disassembling of jalr
......................................................................
arch-riscv: Fix disassembling of jalr
The 'jalr' instruction of 'format Jump' should have an immediate as
offset. This patch fixes the problem.
Note that this is not valid for the other two instructions of the
same format: 'c.jr' and 'c.jalr'.
Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Signed-off-by: Ian Jiang <ianjiang....@gmail.com>
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 11c06aa..a0460b5 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -286,7 +286,10 @@
std::vector<RegId> indices = {%(regs)s};
std::stringstream ss;
ss << mnemonic << ' ';
- ss << registerName(indices[0]);
+ if ((machInst & 0x3) == 0x3)
+ ss << imm << '(' << registerName(indices[0]) << ')';
+ else
+ ss << registerName(indices[0]);
return ss.str();
}
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Gerrit-Change-Number: 33155
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang <ianjiang....@gmail.com>
Gerrit-MessageType: newchange
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