Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33234 )
Change subject: arch-riscv: Fix bug in getting branch target of jalr
......................................................................
arch-riscv: Fix bug in getting branch target of jalr
The 'jalr' instruction is:
jalr rd, offset(rs1) t=pc+4; pc=(x[rs1]+sext(offset))&~1; x[rd]=t
And the branch target address is
pc=(x[rs1]+sext(offset))&~1
When rs1 == rd, x[rs1] will be updated after instruction execution. In
this situation the branch target computed with previous rule is not
correct.
For example, here is a piece of trace with --debug-flags=Exec,IntRegs:
: Setting int reg 0 (0) to 0.
: Reading int reg 1 (1) as 0x12d0f8.
: Setting int reg 1 (1) to 0x1d100.
: jalr ra, -168(ra) : IntAlu : D=0x000000000001d100
And the branch target expected should be (0x12d0f8-168), but not
(0x1d100-168).
This patch fix the problem. First detect if 'jalr' has been executed
or not by comparing the difference between pc and npc. Then, if
executed, use npc as the branch target, else compute branch target
with previous rule. It also applies to the compressed form 'c.jalr'.
Change-Id: I3ced4c259620763acde440bb876c9a2a8e43515c
Signed-off-by: Ian Jiang <ianjiang....@gmail.com>
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 11c06aa..e124ef1 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -275,7 +275,13 @@
%(class_name)s::branchTarget(ThreadContext *tc) const
{
PCState pc = tc->pcState();
- pc.set((tc->readIntReg(_srcRegIdx[0].index()) + imm)&~0x1);
+ Addr pc_addr = pc.pc();
+ Addr npc_addr = pc.npc();
+ if ((pc.compressed() && (npc_addr == pc_addr +
sizeof(MachInst)/2)) ||
+ (!pc.compressed() && (npc_addr == pc_addr + sizeof(MachInst))))
+ pc.set((tc->readIntReg(_srcRegIdx[0].index()) + imm)&~0x1);
+ else
+ pc.set(npc_addr);
return pc;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3ced4c259620763acde440bb876c9a2a8e43515c
Gerrit-Change-Number: 33234
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang <ianjiang....@gmail.com>
Gerrit-MessageType: newchange
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