Emily Brickey has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33397 )
Change subject: cpu-o3: convert rename to new style stats
......................................................................
cpu-o3: convert rename to new style stats
Change-Id: Id34a85e40ad7e83d5805a034df6e0c5ad9b9af82
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
3 files changed, 150 insertions(+), 176 deletions(-)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 47caa67..b11dbbc 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -442,7 +442,6 @@
totalIpc = sum(committedInsts) / numCycles;
this->fetch.regStats();
- this->rename.regStats();
this->iew.regStats();
this->rob.regStats();
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index e3dc3e9..ac955b2 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -133,9 +133,6 @@
/** Returns the name of rename. */
std::string name() const;
- /** Registers statistics. */
- void regStats();
-
/** Registers probes. */
void regProbePoints();
@@ -481,51 +478,62 @@
*/
inline void incrFullStat(const FullSource &source);
- /** Stat for total number of cycles spent squashing. */
- Stats::Scalar renameSquashCycles;
- /** Stat for total number of cycles spent idle. */
- Stats::Scalar renameIdleCycles;
- /** Stat for total number of cycles spent blocking. */
- Stats::Scalar renameBlockCycles;
- /** Stat for total number of cycles spent stalling for a serializing
inst. */
- Stats::Scalar renameSerializeStallCycles;
- /** Stat for total number of cycles spent running normally. */
- Stats::Scalar renameRunCycles;
- /** Stat for total number of cycles spent unblocking. */
- Stats::Scalar renameUnblockCycles;
- /** Stat for total number of renamed instructions. */
- Stats::Scalar renameRenamedInsts;
- /** Stat for total number of squashed instructions that rename
discards. */
- Stats::Scalar renameSquashedInsts;
- /** Stat for total number of times that the ROB starts a stall in
rename. */
- Stats::Scalar renameROBFullEvents;
- /** Stat for total number of times that the IQ starts a stall in
rename. */
- Stats::Scalar renameIQFullEvents;
- /** Stat for total number of times that the LQ starts a stall in
rename. */
- Stats::Scalar renameLQFullEvents;
- /** Stat for total number of times that the SQ starts a stall in
rename. */
- Stats::Scalar renameSQFullEvents;
- /** Stat for total number of times that rename runs out of free
registers
- * to use to rename. */
- Stats::Scalar renameFullRegistersEvents;
- /** Stat for total number of renamed destination registers. */
- Stats::Scalar renameRenamedOperands;
- /** Stat for total number of source register rename lookups. */
- Stats::Scalar renameRenameLookups;
- Stats::Scalar intRenameLookups;
- Stats::Scalar fpRenameLookups;
- Stats::Scalar vecRenameLookups;
- Stats::Scalar vecPredRenameLookups;
- /** Stat for total number of committed renaming mappings. */
- Stats::Scalar renameCommittedMaps;
- /** Stat for total number of mappings that were undone due to a
squash. */
- Stats::Scalar renameUndoneMaps;
- /** Number of serialize instructions handled. */
- Stats::Scalar renamedSerializing;
- /** Number of instructions marked as temporarily serializing. */
- Stats::Scalar renamedTempSerializing;
- /** Number of instructions inserted into skid buffers. */
- Stats::Scalar renameSkidInsts;
+ struct RenameStats : public Stats::Group {
+ RenameStats(Stats::Group *parent);
+
+ /** Stat for total number of cycles spent squashing. */
+ Stats::Scalar squashCycles;
+ /** Stat for total number of cycles spent idle. */
+ Stats::Scalar idleCycles;
+ /** Stat for total number of cycles spent blocking. */
+ Stats::Scalar blockCycles;
+ /** Stat for total number of cycles spent stalling for a
serializing
+ * inst. */
+ Stats::Scalar serializeStallCycles;
+ /** Stat for total number of cycles spent running normally. */
+ Stats::Scalar runCycles;
+ /** Stat for total number of cycles spent unblocking. */
+ Stats::Scalar unblockCycles;
+ /** Stat for total number of renamed instructions. */
+ Stats::Scalar renamedInsts;
+ /** Stat for total number of squashed instructions that rename
+ * discards. */
+ Stats::Scalar squashedInsts;
+ /** Stat for total number of times that the ROB starts a stall in
+ * rename. */
+ Stats::Scalar ROBFullEvents;
+ /** Stat for total number of times that the IQ starts a stall in
+ * rename. */
+ Stats::Scalar IQFullEvents;
+ /** Stat for total number of times that the LQ starts a stall in
+ * rename. */
+ Stats::Scalar LQFullEvents;
+ /** Stat for total number of times that the SQ starts a stall in
+ * rename. */
+ Stats::Scalar SQFullEvents;
+ /** Stat for total number of times that rename runs out of free
+ * registers to use to rename. */
+ Stats::Scalar fullRegistersEvents;
+ /** Stat for total number of renamed destination registers. */
+ Stats::Scalar renamedOperands;
+ /** Stat for total number of source register rename lookups. */
+ Stats::Scalar renameLookups;
+ Stats::Scalar intRenameLookups;
+ Stats::Scalar fpRenameLookups;
+ Stats::Scalar vecRenameLookups;
+ Stats::Scalar vecPredRenameLookups;
+ /** Stat for total number of committed renaming mappings. */
+ Stats::Scalar committedMaps;
+ /** Stat for total number of mappings that were undone due to a
+ * squash. */
+ Stats::Scalar undoneMaps;
+ /** Number of serialize instructions handled. */
+ Stats::Scalar serializing;
+ /** Number of instructions marked as temporarily serializing. */
+ Stats::Scalar tempSerializing;
+ /** Number of instructions inserted into skid buffers. */
+ Stats::Scalar skidInsts;
+ } stats;
};
#endif // __CPU_O3_RENAME_HH__
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 7447764..bab6484 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -64,7 +64,8 @@
commitToRenameDelay(params->commitToRenameDelay),
renameWidth(params->renameWidth),
commitWidth(params->commitWidth),
- numThreads(params->numThreads)
+ numThreads(params->numThreads),
+ stats(_cpu)
{
if (renameWidth > Impl::MaxWidth)
fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
@@ -95,108 +96,74 @@
}
template <class Impl>
-void
-DefaultRename<Impl>::regStats()
+DefaultRename<Impl>::RenameStats::RenameStats(Stats::Group *parent)
+ : Stats::Group(parent, "rename"),
+ ADD_STAT(squashCycles, "Number of cycles rename is squashing"),
+ ADD_STAT(idleCycles, "Number of cycles rename is idle"),
+ ADD_STAT(blockCycles, "Number of cycles rename is blocking"),
+ ADD_STAT(serializeStallCycles, "count of cycles rename stalled"
+ "for serializing inst"),
+ ADD_STAT(runCycles, "Number of cycles rename is running"),
+ ADD_STAT(unblockCycles, "Number of cycles rename is unblocking"),
+ ADD_STAT(renamedInsts, "Number of instructions processed by"
+ " rename"),
+ ADD_STAT(squashedInsts, "Number of squashed instructions"
+ " processed by rename"),
+ ADD_STAT(ROBFullEvents, "Number of times rename has blocked"
+ " due to ROB full"),
+ ADD_STAT(IQFullEvents, "Number of times rename has blocked due"
+ " to IQ full"),
+ ADD_STAT(LQFullEvents, "Number of times rename has blocked due"
+ " to LQ full" ),
+ ADD_STAT(SQFullEvents, "Number of times rename has blocked due"
+ " to SQ full"),
+ ADD_STAT(fullRegistersEvents, "Number of times there has been no"
+ " free registers"),
+ ADD_STAT(renamedOperands, "Number of destination operands rename"
+ " has renamed"),
+ ADD_STAT(renameLookups, "Number of register rename lookups that"
+ " rename has made"),
+ ADD_STAT(intRenameLookups, "Number of integer rename lookups"),
+ ADD_STAT(fpRenameLookups, "Number of floating rename lookups"),
+ ADD_STAT(vecRenameLookups, "Number of vector rename lookups"),
+ ADD_STAT(vecPredRenameLookups, "Number of vector predicate rename"
+ " lookups"),
+ ADD_STAT(committedMaps, "Number of HB maps that are committed"),
+ ADD_STAT(undoneMaps, "Number of HB maps that are undone due to"
+ " squashing"),
+ ADD_STAT(serializing, "count of serializing insts renamed" ),
+ ADD_STAT(tempSerializing, "count of temporary serializing insts"
+ " renamed"),
+ ADD_STAT(skidInsts, "count of insts added to the skid buffer")
{
- renameSquashCycles
- .name(name() + ".SquashCycles")
- .desc("Number of cycles rename is squashing")
- .prereq(renameSquashCycles);
- renameIdleCycles
- .name(name() + ".IdleCycles")
- .desc("Number of cycles rename is idle")
- .prereq(renameIdleCycles);
- renameBlockCycles
- .name(name() + ".BlockCycles")
- .desc("Number of cycles rename is blocking")
- .prereq(renameBlockCycles);
- renameSerializeStallCycles
- .name(name() + ".serializeStallCycles")
- .desc("count of cycles rename stalled for serializing inst")
- .flags(Stats::total);
- renameRunCycles
- .name(name() + ".RunCycles")
- .desc("Number of cycles rename is running")
- .prereq(renameIdleCycles);
- renameUnblockCycles
- .name(name() + ".UnblockCycles")
- .desc("Number of cycles rename is unblocking")
- .prereq(renameUnblockCycles);
- renameRenamedInsts
- .name(name() + ".RenamedInsts")
- .desc("Number of instructions processed by rename")
- .prereq(renameRenamedInsts);
- renameSquashedInsts
- .name(name() + ".SquashedInsts")
- .desc("Number of squashed instructions processed by rename")
- .prereq(renameSquashedInsts);
- renameROBFullEvents
- .name(name() + ".ROBFullEvents")
- .desc("Number of times rename has blocked due to ROB full")
- .prereq(renameROBFullEvents);
- renameIQFullEvents
- .name(name() + ".IQFullEvents")
- .desc("Number of times rename has blocked due to IQ full")
- .prereq(renameIQFullEvents);
- renameLQFullEvents
- .name(name() + ".LQFullEvents")
- .desc("Number of times rename has blocked due to LQ full")
- .prereq(renameLQFullEvents);
- renameSQFullEvents
- .name(name() + ".SQFullEvents")
- .desc("Number of times rename has blocked due to SQ full")
- .prereq(renameSQFullEvents);
- renameFullRegistersEvents
- .name(name() + ".FullRegisterEvents")
- .desc("Number of times there has been no free registers")
- .prereq(renameFullRegistersEvents);
- renameRenamedOperands
- .name(name() + ".RenamedOperands")
- .desc("Number of destination operands rename has renamed")
- .prereq(renameRenamedOperands);
- renameRenameLookups
- .name(name() + ".RenameLookups")
- .desc("Number of register rename lookups that rename has made")
- .prereq(renameRenameLookups);
- renameCommittedMaps
- .name(name() + ".CommittedMaps")
- .desc("Number of HB maps that are committed")
- .prereq(renameCommittedMaps);
- renameUndoneMaps
- .name(name() + ".UndoneMaps")
- .desc("Number of HB maps that are undone due to squashing")
- .prereq(renameUndoneMaps);
- renamedSerializing
- .name(name() + ".serializingInsts")
- .desc("count of serializing insts renamed")
- .flags(Stats::total)
- ;
- renamedTempSerializing
- .name(name() + ".tempSerializingInsts")
- .desc("count of temporary serializing insts renamed")
- .flags(Stats::total)
- ;
- renameSkidInsts
- .name(name() + ".skidInsts")
- .desc("count of insts added to the skid buffer")
- .flags(Stats::total)
- ;
- intRenameLookups
- .name(name() + ".int_rename_lookups")
- .desc("Number of integer rename lookups")
- .prereq(intRenameLookups);
- fpRenameLookups
- .name(name() + ".fp_rename_lookups")
- .desc("Number of floating rename lookups")
- .prereq(fpRenameLookups);
- vecRenameLookups
- .name(name() + ".vec_rename_lookups")
- .desc("Number of vector rename lookups")
- .prereq(vecRenameLookups);
- vecPredRenameLookups
- .name(name() + ".vec_pred_rename_lookups")
- .desc("Number of vector predicate rename lookups")
- .prereq(vecPredRenameLookups);
+ squashCycles.prereq(squashCycles);
+ idleCycles.prereq(idleCycles);
+ blockCycles.prereq(blockCycles);
+ serializeStallCycles.flags(Stats::total);
+ runCycles.prereq(idleCycles);
+ unblockCycles.prereq(unblockCycles);
+
+ renamedInsts.prereq(renamedInsts);
+ squashedInsts.prereq(squashedInsts);
+
+ ROBFullEvents.prereq(ROBFullEvents);
+ IQFullEvents.prereq(IQFullEvents);
+ LQFullEvents.prereq(LQFullEvents);
+ SQFullEvents.prereq(SQFullEvents);
+ fullRegistersEvents.prereq(fullRegistersEvents);
+
+ renamedOperands.prereq(renamedOperands);
+ renameLookups.prereq(renameLookups);
+ intRenameLookups.prereq(intRenameLookups);
+ fpRenameLookups.prereq(fpRenameLookups);
+ vecRenameLookups.prereq(vecRenameLookups);
+ vecPredRenameLookups.prereq(vecPredRenameLookups);
+
+ committedMaps.prereq(committedMaps);
+ undoneMaps.prereq(undoneMaps);
+ serializing.flags(Stats::total);
+ tempSerializing.flags(Stats::total);
+ skidInsts.flags(Stats::total);
}
template <class Impl>
@@ -497,11 +464,11 @@
// check if stall conditions have passed
if (renameStatus[tid] == Blocked) {
- ++renameBlockCycles;
+ ++stats.blockCycles;
} else if (renameStatus[tid] == Squashing) {
- ++renameSquashCycles;
+ ++stats.squashCycles;
} else if (renameStatus[tid] == SerializeStall) {
- ++renameSerializeStallCycles;
+ ++stats.serializeStallCycles;
// If we are currently in SerializeStall and resumeSerialize
// was set, then that means that we are resuming serializing
// this cycle. Tell the previous stages to block.
@@ -556,12 +523,12 @@
DPRINTF(Rename, "[tid:%i] Nothing to do, breaking out early.\n",
tid);
// Should I change status to idle?
- ++renameIdleCycles;
+ ++stats.idleCycles;
return;
} else if (renameStatus[tid] == Unblocking) {
- ++renameUnblockCycles;
+ ++stats.unblockCycles;
} else if (renameStatus[tid] == Running) {
- ++renameRunCycles;
+ ++stats.runCycles;
}
// Will have to do a different calculation for the number of free
@@ -677,7 +644,7 @@
"instruction %i with PC %s is squashed, skipping.\n",
tid, inst->seqNum, inst->pcState());
- ++renameSquashedInsts;
+ ++stats.squashedInsts;
// Decrement how many instructions are available.
--insts_available;
@@ -703,7 +670,7 @@
" lack of free physical registers to rename to.\n");
blockThisCycle = true;
insts_to_rename.push_front(inst);
- ++renameFullRegistersEvents;
+ ++stats.fullRegistersEvents;
break;
}
@@ -723,10 +690,10 @@
DPRINTF(Rename, "Serialize before instruction encountered.\n");
if (!inst->isTempSerializeBefore()) {
- renamedSerializing++;
+ stats.serializing++;
inst->setSerializeHandled();
} else {
- renamedTempSerializing++;
+ stats.tempSerializing++;
}
// Change status over to SerializeStall so that other stages
know
@@ -742,7 +709,7 @@
!inst->isSerializeHandled()) {
DPRINTF(Rename, "Serialize after instruction encountered.\n");
- renamedSerializing++;
+ stats.serializing++;
inst->setSerializeHandled();
@@ -776,7 +743,7 @@
}
instsInProgress[tid] += renamed_insts;
- renameRenamedInsts += renamed_insts;
+ stats.renamedInsts += renamed_insts;
// If we wrote to the time buffer, record this.
if (toIEWIndex) {
@@ -811,7 +778,7 @@
DPRINTF(Rename, "[tid:%i] Inserting [sn:%llu] PC: %s into Rename "
"skidBuffer\n", tid, inst->seqNum, inst->pcState());
- ++renameSkidInsts;
+ ++stats.skidInsts;
skidBuffer[tid].push_back(inst);
}
@@ -1000,7 +967,7 @@
historyBuffer[tid].erase(hb_it++);
- ++renameUndoneMaps;
+ ++stats.undoneMaps;
}
// Check if we need to change vector renaming mode after squashing
@@ -1052,7 +1019,7 @@
freeList->addReg(hb_it->prevPhysReg);
}
- ++renameCommittedMaps;
+ ++stats.committedMaps;
historyBuffer[tid].erase(hb_it--);
}
@@ -1075,17 +1042,17 @@
renamed_reg = map->lookup(tc->flattenRegId(src_reg));
switch (src_reg.classValue()) {
case IntRegClass:
- intRenameLookups++;
+ stats.intRenameLookups++;
break;
case FloatRegClass:
- fpRenameLookups++;
+ stats.fpRenameLookups++;
break;
case VecRegClass:
case VecElemClass:
- vecRenameLookups++;
+ stats.vecRenameLookups++;
break;
case VecPredRegClass:
- vecPredRenameLookups++;
+ stats.vecPredRenameLookups++;
break;
case CCRegClass:
case MiscRegClass:
@@ -1121,7 +1088,7 @@
renamed_reg->className());
}
- ++renameRenameLookups;
+ ++stats.renameLookups;
}
}
@@ -1175,7 +1142,7 @@
rename_result.first,
rename_result.second);
- ++renameRenamedOperands;
+ ++stats.renamedOperands;
}
}
@@ -1445,16 +1412,16 @@
{
switch (source) {
case ROB:
- ++renameROBFullEvents;
+ ++stats.ROBFullEvents;
break;
case IQ:
- ++renameIQFullEvents;
+ ++stats.IQFullEvents;
break;
case LQ:
- ++renameLQFullEvents;
+ ++stats.LQFullEvents;
break;
case SQ:
- ++renameSQFullEvents;
+ ++stats.SQFullEvents;
break;
default:
panic("Rename full stall stat should be incremented for a
reason!");
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33397
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id34a85e40ad7e83d5805a034df6e0c5ad9b9af82
Gerrit-Change-Number: 33397
Gerrit-PatchSet: 1
Gerrit-Owner: Emily Brickey <esbric...@ucdavis.edu>
Gerrit-MessageType: newchange
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