Eden Avivi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33508 )
Change subject: cpu: MasterID to UniqueID
......................................................................
cpu: MasterID to UniqueID
Change-Id: I68d9a896f1ed9892a10ae222341716fb1d8ad467
---
M src/cpu/base.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/testers/directedtest/DirectedGenerator.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/testers/traffic_gen/base_gen.cc
M src/cpu/testers/traffic_gen/base_gen.hh
M src/cpu/testers/traffic_gen/dram_gen.cc
M src/cpu/testers/traffic_gen/dram_gen.hh
M src/cpu/testers/traffic_gen/dram_rot_gen.hh
M src/cpu/testers/traffic_gen/exit_gen.hh
M src/cpu/testers/traffic_gen/idle_gen.hh
M src/cpu/testers/traffic_gen/linear_gen.hh
M src/cpu/testers/traffic_gen/random_gen.hh
M src/cpu/testers/traffic_gen/trace_gen.hh
M src/cpu/trace/trace_cpu.hh
20 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 5c0c709..187e759 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -124,10 +124,10 @@
const uint32_t _socketId;
/** instruction side request id that must be placed in all requests */
- MasterID _instMasterId;
+ UniqueID _instMasterId;
/** data side request id that must be placed in all requests */
- MasterID _dataMasterId;
+ UniqueID _dataMasterId;
/** An intrenal representation of a task identifier within gem5. This
is
* used so the CPU can add which taskId (which is an internal
representation
@@ -182,9 +182,9 @@
uint32_t socketId() const { return _socketId; }
/** Reads this CPU's unique data requestor ID */
- MasterID dataMasterId() const { return _dataMasterId; }
+ UniqueID dataMasterId() const { return _dataMasterId; }
/** Reads this CPU's unique instruction requestor ID */
- MasterID instMasterId() const { return _instMasterId; }
+ UniqueID instMasterId() const { return _instMasterId; }
/**
* Get a port on this CPU. All CPUs have a data and
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b98cbaa..d53844c 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -441,7 +441,7 @@
uint32_t socketId() const { return cpu->socketId(); }
/** Read this CPU's data requestor ID */
- MasterID masterId() const { return cpu->dataMasterId(); }
+ UniqueID masterId() const { return cpu->dataMasterId(); }
/** Read this context's system-wide ID **/
ContextID contextId() const { return thread->contextId(); }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3c04064..0598e30 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -89,7 +89,7 @@
using VecRegContainer = TheISA::VecRegContainer;
/** id attached to all issued requests */
- MasterID masterId;
+ UniqueID masterId;
public:
void init() override;
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 9ef3b0c..b9892f4 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -456,7 +456,7 @@
*/
void
setVirt(Addr vaddr, unsigned size, Request::Flags flags_,
- MasterID mid, Addr pc)
+ UniqueID mid, Addr pc)
{
request()->setVirt(vaddr, size, flags_, mid, pc);
}
diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh
b/src/cpu/testers/directedtest/DirectedGenerator.hh
index 2d03372..994a276 100644
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh
@@ -49,7 +49,7 @@
protected:
int m_num_cpus;
- MasterID masterId;
+ UniqueID masterId;
RubyDirectedTester* m_directed_tester;
};
diff --git
a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
index 524a960..ebd6469 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
@@ -130,7 +130,7 @@
const Cycles responseLimit;
- MasterID masterId;
+ UniqueID masterId;
void completeRequest(PacketPtr pkt);
diff --git a/src/cpu/testers/memtest/memtest.hh
b/src/cpu/testers/memtest/memtest.hh
index 86b27a4..a0dd748 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -127,7 +127,7 @@
const unsigned percentUncacheable;
/** Request id for all generated traffic */
- MasterID masterId;
+ UniqueID masterId;
unsigned int id;
diff --git a/src/cpu/testers/rubytest/RubyTester.hh
b/src/cpu/testers/rubytest/RubyTester.hh
index e63729a..2a31ae5 100644
--- a/src/cpu/testers/rubytest/RubyTester.hh
+++ b/src/cpu/testers/rubytest/RubyTester.hh
@@ -117,11 +117,11 @@
void print(std::ostream& out) const;
bool getCheckFlush() { return m_check_flush; }
- MasterID masterId() { return _masterId; }
+ UniqueID masterId() { return _masterId; }
protected:
EventFunctionWrapper checkStartEvent;
- MasterID _masterId;
+ UniqueID _masterId;
private:
void hitCallback(NodeID proc, SubBlock* data);
diff --git a/src/cpu/testers/traffic_gen/base.hh
b/src/cpu/testers/traffic_gen/base.hh
index 17b1aa1..8ae1f2e 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -299,9 +299,9 @@
virtual std::shared_ptr<BaseGen> nextGenerator() = 0;
/**
- * MasterID used in generated requests.
+ * UniqueID used in generated requests.
*/
- const MasterID masterID;
+ const UniqueID masterID;
/** Currently active generator */
std::shared_ptr<BaseGen> activeGenerator;
diff --git a/src/cpu/testers/traffic_gen/base_gen.cc
b/src/cpu/testers/traffic_gen/base_gen.cc
index d5cdf71..e1518b7 100644
--- a/src/cpu/testers/traffic_gen/base_gen.cc
+++ b/src/cpu/testers/traffic_gen/base_gen.cc
@@ -46,7 +46,7 @@
#include "debug/TrafficGen.hh"
#include "sim/system.hh"
-BaseGen::BaseGen(SimObject &obj, MasterID master_id, Tick _duration)
+BaseGen::BaseGen(SimObject &obj, UniqueID master_id, Tick _duration)
: _name(obj.name()), masterID(master_id),
duration(_duration)
{
@@ -76,7 +76,7 @@
}
StochasticGen::StochasticGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ UniqueID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/base_gen.hh
b/src/cpu/testers/traffic_gen/base_gen.hh
index 0f51b6c..78ce857 100644
--- a/src/cpu/testers/traffic_gen/base_gen.hh
+++ b/src/cpu/testers/traffic_gen/base_gen.hh
@@ -62,8 +62,8 @@
/** Name to use for status and debug printing */
const std::string _name;
- /** The MasterID used for generating requests */
- const MasterID masterID;
+ /** The UniqueID used for generating requests */
+ const UniqueID masterID;
/**
* Generate a new request and associated packet
@@ -85,10 +85,10 @@
* Create a base generator.
*
* @param obj simobject owning the generator
- * @param master_id MasterID set on each request
+ * @param master_id UniqueID set on each request
* @param _duration duration of this state before transitioning
*/
- BaseGen(SimObject &obj, MasterID master_id, Tick _duration);
+ BaseGen(SimObject &obj, UniqueID master_id, Tick _duration);
virtual ~BaseGen() { }
@@ -133,7 +133,7 @@
{
public:
StochasticGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ UniqueID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/dram_gen.cc
b/src/cpu/testers/traffic_gen/dram_gen.cc
index 0534a8a..5489df0 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.cc
+++ b/src/cpu/testers/traffic_gen/dram_gen.cc
@@ -45,7 +45,7 @@
#include "enums/AddrMap.hh"
DramGen::DramGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ UniqueID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/dram_gen.hh
b/src/cpu/testers/traffic_gen/dram_gen.hh
index 081ca24..29aab3b 100644
--- a/src/cpu/testers/traffic_gen/dram_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_gen.hh
@@ -64,7 +64,7 @@
* Create a DRAM address sequence generator.
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param master_id UniqueID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
@@ -83,7 +83,7 @@
* assumes single channel system
*/
DramGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ UniqueID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.hh
b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
index bb53d49..3b79bb8 100644
--- a/src/cpu/testers/traffic_gen/dram_rot_gen.hh
+++ b/src/cpu/testers/traffic_gen/dram_rot_gen.hh
@@ -63,7 +63,7 @@
* 3) Ranks per channel
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param master_id UniqueID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
@@ -82,7 +82,7 @@
* @param addr_mapping Address mapping to be used,
* assumes single channel system
*/
- DramRotGen(SimObject &obj, MasterID master_id, Tick _duration,
+ DramRotGen(SimObject &obj, UniqueID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/exit_gen.hh
b/src/cpu/testers/traffic_gen/exit_gen.hh
index ec863f7..933711d 100644
--- a/src/cpu/testers/traffic_gen/exit_gen.hh
+++ b/src/cpu/testers/traffic_gen/exit_gen.hh
@@ -54,7 +54,7 @@
public:
- ExitGen(SimObject &obj, MasterID master_id, Tick _duration)
+ ExitGen(SimObject &obj, UniqueID master_id, Tick _duration)
: BaseGen(obj, master_id, _duration)
{ }
diff --git a/src/cpu/testers/traffic_gen/idle_gen.hh
b/src/cpu/testers/traffic_gen/idle_gen.hh
index 761b717..085f2b9 100644
--- a/src/cpu/testers/traffic_gen/idle_gen.hh
+++ b/src/cpu/testers/traffic_gen/idle_gen.hh
@@ -56,7 +56,7 @@
public:
- IdleGen(SimObject &obj, MasterID master_id, Tick _duration)
+ IdleGen(SimObject &obj, UniqueID master_id, Tick _duration)
: BaseGen(obj, master_id, _duration)
{ }
diff --git a/src/cpu/testers/traffic_gen/linear_gen.hh
b/src/cpu/testers/traffic_gen/linear_gen.hh
index b6f4282..9ae5b48 100644
--- a/src/cpu/testers/traffic_gen/linear_gen.hh
+++ b/src/cpu/testers/traffic_gen/linear_gen.hh
@@ -67,7 +67,7 @@
* time.
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param master_id UniqueID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
@@ -79,7 +79,7 @@
* @param data_limit Upper limit on how much data to read/write
*/
LinearGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ UniqueID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/random_gen.hh
b/src/cpu/testers/traffic_gen/random_gen.hh
index ba398a9..d824624 100644
--- a/src/cpu/testers/traffic_gen/random_gen.hh
+++ b/src/cpu/testers/traffic_gen/random_gen.hh
@@ -75,7 +75,7 @@
* @param data_limit Upper limit on how much data to read/write
*/
RandomGen(SimObject &obj,
- MasterID master_id, Tick _duration,
+ UniqueID master_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
diff --git a/src/cpu/testers/traffic_gen/trace_gen.hh
b/src/cpu/testers/traffic_gen/trace_gen.hh
index fe386d8..48af3da 100644
--- a/src/cpu/testers/traffic_gen/trace_gen.hh
+++ b/src/cpu/testers/traffic_gen/trace_gen.hh
@@ -148,12 +148,12 @@
* Create a trace generator.
*
* @param obj SimObject owning this sequence generator
- * @param master_id MasterID related to the memory requests
+ * @param master_id UniqueID related to the memory requests
* @param _duration duration of this state before transitioning
* @param trace_file File to read the transactions from
* @param addr_offset Positive offset to add to trace address
*/
- TraceGen(SimObject &obj, MasterID master_id, Tick _duration,
+ TraceGen(SimObject &obj, UniqueID master_id, Tick _duration,
const std::string& trace_file, Addr addr_offset)
: BaseGen(obj, master_id, _duration),
trace(trace_file),
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index cd292fb..ec4e07b 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -321,11 +321,11 @@
/** Port to connect to L1 data cache. */
DcachePort dcachePort;
- /** Master id for instruction read requests. */
- const MasterID instMasterID;
+ /** Unique id for instruction read requests. */
+ const UniqueID instMasterID;
- /** Master id for data read and write requests. */
- const MasterID dataMasterID;
+ /** Unique id for data read and write requests. */
+ const UniqueID dataMasterID;
/** File names for input instruction and data traces. */
std::string instTraceFile, dataTraceFile;
@@ -423,7 +423,7 @@
public:
/* Constructor */
FixedRetryGen(TraceCPU& _owner, const std::string& _name,
- RequestPort& _port, MasterID master_id,
+ RequestPort& _port, UniqueID master_id,
const std::string& trace_file)
: owner(_owner),
port(_port),
@@ -503,8 +503,8 @@
/** Reference of the port to be used to issue memory requests. */
RequestPort& port;
- /** MasterID used for the requests being sent. */
- const MasterID masterID;
+ /** UniqueID used for the requests being sent. */
+ const UniqueID masterID;
/** Input stream used for reading the input trace file. */
InputStream trace;
@@ -847,7 +847,7 @@
public:
/* Constructor */
ElasticDataGen(TraceCPU& _owner, const std::string& _name,
- RequestPort& _port, MasterID master_id,
+ RequestPort& _port, UniqueID master_id,
const std::string& trace_file, TraceCPUParams *params)
: owner(_owner),
port(_port),
@@ -986,8 +986,8 @@
/** Reference of the port to be used to issue memory requests. */
RequestPort& port;
- /** MasterID used for the requests being sent. */
- const MasterID masterID;
+ /** UniqueID used for the requests being sent. */
+ const UniqueID masterID;
/** Input stream used for reading the input trace file. */
InputStream trace;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33508
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I68d9a896f1ed9892a10ae222341716fb1d8ad467
Gerrit-Change-Number: 33508
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi <eav...@ucdavis.edu>
Gerrit-MessageType: newchange
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