Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33530 )
Change subject: dev-arm: Update instances of masterId - smmu
......................................................................
dev-arm: Update instances of masterId - smmu
smmu files
Change-Id: If766fcc7b6a06420215e814e9a94bfd33b704a0c
---
M src/dev/arm/SMMUv3.py
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_ports.hh
M src/dev/arm/smmu_v3_proc.cc
M src/dev/arm/smmu_v3_slaveifc.cc
M src/dev/arm/smmu_v3_slaveifc.hh
M src/dev/arm/smmu_v3_transl.cc
8 files changed, 111 insertions(+), 103 deletions(-)
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 0b9ab21..ff13139 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -43,9 +43,16 @@
type = 'SMMUv3SlaveInterface'
cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'
- slave = ResponsePort('Device port')
- ats_master = RequestPort('ATS master port')
- ats_slave = ResponsePort('ATS slave port')
+ responder = ResponsePort('Device port')
+ slave = DeprecatedParam(responder, '`slave` is now called
`responder`')
+ ats_mem_side = RequestPort('ATS mem_side port,'
+ 'sends requests and receives responses')
+ ats_master = DeprecatedParam(ats_mem_side,
+ '`ats_master` is now called
`ats_mem_side`')
+ ats_cpu_side = ResponsePort('ATS cpu_side port,'
+ 'sends responses and receives requests')
+ ats_slave = DeprecatedParam(ats_cpu_side,
+ '`ats_slave` is now called `ats_cpu_side`')
port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
@@ -74,18 +81,19 @@
type = 'SMMUv3'
cxx_header = 'dev/arm/smmu_v3.hh'
- master = RequestPort('Master port')
- master_walker = RequestPort(
- 'Master port for SMMU initiated HWTW requests (optional)')
+ requestor = RequestPort('Request port')
+ requestor_walker = RequestPort(
+ 'Request port for SMMU initiated HWTW requests (optional)')
control = ResponsePort(
'Control port for accessing memory-mapped registers')
sample_period = Param.Clock('10us', 'Stats sample period')
reg_map = Param.AddrRange('Address range for control registers')
system = Param.System(Parent.any, "System this device is part of")
- slave_interfaces = VectorParam.SMMUv3SlaveInterface([], "Slave
interfaces")
+ responder_interfaces = VectorParam.SMMUv3SlaveInterface([],
+ "Responder interfaces")
- # SLAVE INTERFACE<->SMMU link parameters
+ # RESPONDER INTERFACE<->SMMU link parameters
ifc_smmu_lat = Param.Cycles(8, 'IFC to SMMU communication latency')
smmu_ifc_lat = Param.Cycles(8, 'SMMU to IFC communication latency')
@@ -93,8 +101,8 @@
xlate_slots = Param.Unsigned(64, 'SMMU translation slots')
ptw_slots = Param.Unsigned(16, 'SMMU page table walk slots')
- master_port_width = Param.Unsigned(16,
- 'Master port width in bytes (= 1 beat)')
+ request_port_width = Param.Unsigned(16,
+ 'Request port width in bytes (= 1 beat)')
tlb_entries = Param.Unsigned(2048, 'TLB size (entries)')
tlb_assoc = Param.Unsigned(4, 'TLB associativity (0=full)')
@@ -185,23 +193,23 @@
def connect(self, device):
"""
- Helper method used to connect the SMMU. The master could
+ Helper method used to connect the SMMU. The requestor could
be either a dma port (if the SMMU is attached directly to a
- dma device), or to a master port (this is the case where the SMMU
+ dma device), or to a request port (this is the case where the SMMU
is attached to a bridge).
"""
- slave_interface = SMMUv3SlaveInterface()
+ responder_interface = SMMUv3SlaveInterface()
- if hasattr(device, "master"):
- slave_interface.slave = device.master
+ if hasattr(device, "requestor"):
+ responder_interface.responder = device.requestor
elif hasattr(device, "dma"):
- slave_interface.slave = device.dma
+ responder_interface.responder = device.dma
else:
print("Unable to attach SMMUv3\n")
sys.exit(1)
- self.slave_interfaces.append(slave_interface)
+ self.responder_interfaces.append(responder_interface)
# Storing a reference to the smmu to be used when generating
# the binding in the device DTB.
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index d3d8a53..2822cb9 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -119,14 +119,14 @@
// store an unallowed values or if the are configuration conflicts.
warn("SMMUv3 IDx register values unchecked\n");
- for (auto ifc : slaveInterfaces)
+ for (auto ifc : respInterfaces)
ifc->setSMMU(this);
}
bool
SMMUv3::masterRecvTimingResp(PacketPtr pkt)
{
- DPRINTF(SMMUv3, "[t] master resp addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] requestor resp addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
// @todo: We need to pay for this and not just zero it out
@@ -150,7 +150,7 @@
assert(a.type==ACTION_SEND_REQ || a.type==ACTION_SEND_REQ_FINAL);
- DPRINTF(SMMUv3, "[t] master retr addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] requestor retr addr=%#x size=%#x\n",
a.pkt->getAddr(), a.pkt->getSize());
if (!requestPort.sendTimingReq(a.pkt))
@@ -160,9 +160,9 @@
/*
* ACTION_SEND_REQ_FINAL means that we have just forwarded the
packet
- * on the master interface; this means that we no longer hold on to
+ * on the requestor interface; this means that we no longer hold
on to
* that transaction and therefore can accept a new one.
- * If the slave port was stalled then unstall it (send retry).
+ * If the response port was stalled then unstall it (send retry).
*/
if (a.type == ACTION_SEND_REQ_FINAL)
scheduleSlaveRetries();
@@ -172,7 +172,7 @@
bool
SMMUv3::masterTableWalkRecvTimingResp(PacketPtr pkt)
{
- DPRINTF(SMMUv3, "[t] master HWTW resp addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] requestor HWTW resp addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
// @todo: We need to pay for this and not just zero it out
@@ -197,10 +197,10 @@
assert(a.type==ACTION_SEND_REQ);
- DPRINTF(SMMUv3, "[t] master HWTW retr addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] requestor HWTW retr addr=%#x size=%#x\n",
a.pkt->getAddr(), a.pkt->getSize());
- if (!masterTableWalkPort.sendTimingReq(a.pkt))
+ if (!requestTableWalkPort.sendTimingReq(a.pkt))
break;
packetsTableWalkToRetry.pop();
@@ -210,7 +210,7 @@
void
SMMUv3::scheduleSlaveRetries()
{
- for (auto ifc : slaveInterfaces) {
+ for (auto ifc : respInterfaces) {
ifc->scheduleDeviceRetry();
}
}
@@ -243,7 +243,7 @@
// enabled. Otherwise, fall through and handle same as the
final
// ACTION_SEND_REQ_FINAL request.
if (tableWalkPortEnable) {
- delay += masterTableWalkPort.sendAtomic(action.pkt);
+ delay += requestTableWalkPort.sendAtomic(action.pkt);
pkt = action.pkt;
break;
}
@@ -289,14 +289,14 @@
if (tableWalkPortEnable) {
action.pkt->pushSenderState(proc);
- DPRINTF(SMMUv3, "[t] master HWTW req addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] requestor HWTW req addr=%#x
size=%#x\n",
action.pkt->getAddr(), action.pkt->getSize());
if (packetsTableWalkToRetry.empty()
- && masterTableWalkPort.sendTimingReq(action.pkt)) {
+ && requestTableWalkPort.sendTimingReq(action.pkt))
{
scheduleSlaveRetries();
} else {
- DPRINTF(SMMUv3, "[t] master HWTW req needs retry,"
+ DPRINTF(SMMUv3, "[t] requestor HWTW req needs retry,"
" qlen=%d\n", packetsTableWalkToRetry.size());
packetsTableWalkToRetry.push(action);
}
@@ -307,14 +307,14 @@
case ACTION_SEND_REQ_FINAL:
action.pkt->pushSenderState(proc);
- DPRINTF(SMMUv3, "[t] master req addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] requestor req addr=%#x size=%#x\n",
action.pkt->getAddr(), action.pkt->getSize());
if (packetsToRetry.empty() &&
requestPort.sendTimingReq(action.pkt)) {
scheduleSlaveRetries();
} else {
- DPRINTF(SMMUv3, "[t] master req needs retry, qlen=%d\n",
+ DPRINTF(SMMUv3, "[t] requestor req needs retry,
qlen=%d\n",
packetsToRetry.size());
packetsToRetry.push(action);
}
@@ -325,7 +325,7 @@
// @todo: We need to pay for this and not just zero it out
action.pkt->headerDelay = action.pkt->payloadDelay = 0;
- DPRINTF(SMMUv3, "[t] slave resp addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] responder resp addr=%#x size=%#x\n",
action.pkt->getAddr(),
action.pkt->getSize());
@@ -339,7 +339,7 @@
// @todo: We need to pay for this and not just zero it out
action.pkt->headerDelay = action.pkt->payloadDelay = 0;
- DPRINTF(SMMUv3, "[t] ATS slave resp addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] ATS responder resp addr=%#x size=%#x\n",
action.pkt->getAddr(), action.pkt->getSize());
assert(action.ifc);
@@ -395,9 +395,9 @@
DPRINTF(SMMUv3, "CMD_CFGI_STE sid=%#x\n", cmd.dw0.sid);
configCache.invalidateSID(cmd.dw0.sid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateSID(cmd.dw0.sid);
- slave_interface->mainTLB->invalidateSID(cmd.dw0.sid);
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateSID(cmd.dw0.sid);
+ resp_interface->mainTLB->invalidateSID(cmd.dw0.sid);
}
break;
}
@@ -410,9 +410,9 @@
DPRINTF(SMMUv3, "CMD_CFGI_ALL\n");
configCache.invalidateAll();
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateAll();
- slave_interface->mainTLB->invalidateAll();
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateAll();
+ resp_interface->mainTLB->invalidateAll();
}
} else {
DPRINTF(SMMUv3, "CMD_CFGI_STE_RANGE\n");
@@ -421,9 +421,9 @@
for (auto sid = start_sid; sid <= end_sid; sid++) {
configCache.invalidateSID(sid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateSID(sid);
- slave_interface->mainTLB->invalidateSID(sid);
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateSID(sid);
+ resp_interface->mainTLB->invalidateSID(sid);
}
}
}
@@ -435,10 +435,10 @@
cmd.dw0.sid, cmd.dw0.ssid);
configCache.invalidateSSID(cmd.dw0.sid, cmd.dw0.ssid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateSSID(
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateSSID(
cmd.dw0.sid, cmd.dw0.ssid);
- slave_interface->mainTLB->invalidateSSID(
+ resp_interface->mainTLB->invalidateSSID(
cmd.dw0.sid, cmd.dw0.ssid);
}
break;
@@ -448,18 +448,18 @@
DPRINTF(SMMUv3, "CMD_CFGI_CD_ALL sid=%#x\n", cmd.dw0.sid);
configCache.invalidateSID(cmd.dw0.sid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateSID(cmd.dw0.sid);
- slave_interface->mainTLB->invalidateSID(cmd.dw0.sid);
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateSID(cmd.dw0.sid);
+ resp_interface->mainTLB->invalidateSID(cmd.dw0.sid);
}
break;
}
case CMD_TLBI_NH_ALL: {
DPRINTF(SMMUv3, "CMD_TLBI_NH_ALL vmid=%#x\n", cmd.dw0.vmid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateVMID(cmd.dw0.vmid);
- slave_interface->mainTLB->invalidateVMID(cmd.dw0.vmid);
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateVMID(cmd.dw0.vmid);
+ resp_interface->mainTLB->invalidateVMID(cmd.dw0.vmid);
}
tlb.invalidateVMID(cmd.dw0.vmid);
walkCache.invalidateVMID(cmd.dw0.vmid);
@@ -469,10 +469,10 @@
case CMD_TLBI_NH_ASID: {
DPRINTF(SMMUv3, "CMD_TLBI_NH_ASID asid=%#x vmid=%#x\n",
cmd.dw0.asid, cmd.dw0.vmid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateASID(
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateASID(
cmd.dw0.asid, cmd.dw0.vmid);
- slave_interface->mainTLB->invalidateASID(
+ resp_interface->mainTLB->invalidateASID(
cmd.dw0.asid, cmd.dw0.vmid);
}
tlb.invalidateASID(cmd.dw0.asid, cmd.dw0.vmid);
@@ -484,10 +484,10 @@
const Addr addr = cmd.addr();
DPRINTF(SMMUv3, "CMD_TLBI_NH_VAA va=%#08x vmid=%#x\n",
addr, cmd.dw0.vmid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateVAA(
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateVAA(
addr, cmd.dw0.vmid);
- slave_interface->mainTLB->invalidateVAA(
+ resp_interface->mainTLB->invalidateVAA(
addr, cmd.dw0.vmid);
}
tlb.invalidateVAA(addr, cmd.dw0.vmid);
@@ -500,10 +500,10 @@
const Addr addr = cmd.addr();
DPRINTF(SMMUv3, "CMD_TLBI_NH_VA va=%#08x asid=%#x vmid=%#x\n",
addr, cmd.dw0.asid, cmd.dw0.vmid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateVA(
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateVA(
addr, cmd.dw0.asid, cmd.dw0.vmid);
- slave_interface->mainTLB->invalidateVA(
+ resp_interface->mainTLB->invalidateVA(
addr, cmd.dw0.asid, cmd.dw0.vmid);
}
tlb.invalidateVA(addr, cmd.dw0.asid, cmd.dw0.vmid);
@@ -528,9 +528,9 @@
case CMD_TLBI_S12_VMALL: {
DPRINTF(SMMUv3, "CMD_TLBI_S12_VMALL vmid=%#x\n", cmd.dw0.vmid);
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateVMID(cmd.dw0.vmid);
- slave_interface->mainTLB->invalidateVMID(cmd.dw0.vmid);
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateVMID(cmd.dw0.vmid);
+ resp_interface->mainTLB->invalidateVMID(cmd.dw0.vmid);
}
tlb.invalidateVMID(cmd.dw0.vmid);
ipaCache.invalidateVMID(cmd.dw0.vmid);
@@ -540,9 +540,9 @@
case CMD_TLBI_NSNH_ALL: {
DPRINTF(SMMUv3, "CMD_TLBI_NSNH_ALL\n");
- for (auto slave_interface : slaveInterfaces) {
- slave_interface->microTLB->invalidateAll();
- slave_interface->mainTLB->invalidateAll();
+ for (auto resp_interface : respInterfaces) {
+ resp_interface->microTLB->invalidateAll();
+ resp_interface->mainTLB->invalidateAll();
}
tlb.invalidateAll();
ipaCache.invalidateAll();
@@ -719,15 +719,15 @@
{
// make sure both sides are connected and have the same block size
if (!requestPort.isConnected())
- fatal("Master port is not connected.\n");
+ fatal("Request port is not connected.\n");
- // If the second master port is connected for the table walks, enable
+ // If the second request port is connected for the table walks, enable
// the mode to send table walks through this port instead
- if (masterTableWalkPort.isConnected())
+ if (requestTableWalkPort.isConnected())
tableWalkPortEnable = true;
- // notify the master side of our address ranges
- for (auto ifc : slaveInterfaces) {
+ // notify the request side of our address ranges
+ for (auto ifc : respInterfaces) {
ifc->sendRange();
}
@@ -742,10 +742,10 @@
using namespace Stats;
- for (size_t i = 0; i < slaveInterfaces.size(); i++) {
- slaveInterfaces[i]->microTLB->regStats(
+ for (size_t i = 0; i < respInterfaces.size(); i++) {
+ respInterfaces[i]->microTLB->regStats(
csprintf("%s.utlb%d", name(), i));
- slaveInterfaces[i]->mainTLB->regStats(
+ respInterfaces[i]->mainTLB->regStats(
csprintf("%s.maintlb%d", name(), i));
}
@@ -816,7 +816,7 @@
Port&
SMMUv3::getPort(const std::string &name, PortID id)
{
- if (name == "master") {
+ if (name == "requestor") {
return requestPort;
} else if (name == "requestor_walker") {
return requestTableWalkPort;
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index 76a8c8f..6697dbf 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -88,10 +88,10 @@
friend class SMMUv3SlaveInterface;
const System &system;
- const MasterID masterId;
+ const MasterID _id;
SMMUMasterPort requestPort;
- SMMUMasterTableWalkPort masterTableWalkPort;
+ SMMUMasterTableWalkPort requestTableWalkPort;
SMMUControlPort controlPort;
ARMArchTLB tlb;
diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index ee68bbb..35293bb 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -57,7 +57,7 @@
virtual ~SMMUMasterPort() {}
};
-// Separate master port to send MMU initiated requests on
+// Separate request port to send MMU initiated requests on
class SMMUMasterTableWalkPort : public RequestPort
{
protected:
diff --git a/src/dev/arm/smmu_v3_proc.cc b/src/dev/arm/smmu_v3_proc.cc
index 5da7f26..e30c00a 100644
--- a/src/dev/arm/smmu_v3_proc.cc
+++ b/src/dev/arm/smmu_v3_proc.cc
@@ -76,7 +76,7 @@
a.type = ACTION_SEND_REQ;
RequestPtr req = std::make_shared<Request>(
- addr, size, 0, smmu.masterId);
+ addr, size, 0, smmu._id);
req->taskId(ContextSwitchTaskId::DMA);
@@ -109,7 +109,7 @@
a.type = ACTION_SEND_REQ;
RequestPtr req = std::make_shared<Request>(
- addr, size, 0, smmu.masterId);
+ addr, size, 0, smmu._id);
req->taskId(ContextSwitchTaskId::DMA);
diff --git a/src/dev/arm/smmu_v3_slaveifc.cc
b/src/dev/arm/smmu_v3_slaveifc.cc
index 88f190f..03a38f6 100644
--- a/src/dev/arm/smmu_v3_slaveifc.cc
+++ b/src/dev/arm/smmu_v3_slaveifc.cc
@@ -79,11 +79,11 @@
SMMUv3SlaveInterface::sendRange()
{
if (responsePort->isConnected()) {
- inform("Slave port is connected to %s\n", responsePort->getPeer());
+ inform("Response port is connected to %s\n",
responsePort->getPeer());
responsePort->sendRangeChange();
} else {
- fatal("Slave port is not connected.\n");
+ fatal("Response port is not connected.\n");
}
}
@@ -110,7 +110,7 @@
void
SMMUv3SlaveInterface::schedAtsTimingResp(PacketPtr pkt)
{
- atsSlavePort.schedTimingResp(pkt, nextCycle());
+ atsResponsePort.schedTimingResp(pkt, nextCycle());
if (atsDeviceNeedsRetry) {
atsDeviceNeedsRetry = false;
@@ -169,7 +169,7 @@
Tick
SMMUv3SlaveInterface::atsSlaveRecvAtomic(PacketPtr pkt)
{
- DPRINTF(SMMUv3, "[a] ATS slave req addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[a] ATS responder req addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
std::string proc_name = csprintf("%s.atsport", name());
@@ -187,7 +187,7 @@
bool
SMMUv3SlaveInterface::atsSlaveRecvTimingReq(PacketPtr pkt)
{
- DPRINTF(SMMUv3, "[t] ATS slave req addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] ATS responder req addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
// @todo: We need to pay for this and not just zero it out
@@ -212,7 +212,7 @@
bool
SMMUv3SlaveInterface::atsMasterRecvTimingResp(PacketPtr pkt)
{
- DPRINTF(SMMUv3, "[t] ATS master resp addr=%#x size=%#x\n",
+ DPRINTF(SMMUv3, "[t] ATS mem_side resp addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
// @todo: We need to pay for this and not just zero it out
@@ -236,14 +236,14 @@
SMMUv3SlaveInterface::atsSendDeviceRetry()
{
DPRINTF(SMMUv3, "ATS retry\n");
- atsSlavePort.sendRetryReq();
+ atsResponsePort.sendRetryReq();
}
void
SMMUv3SlaveInterface::scheduleDeviceRetry()
{
if (deviceNeedsRetry && !sendDeviceRetryEvent.scheduled()) {
- DPRINTF(SMMUv3, "sched slave retry\n");
+ DPRINTF(SMMUv3, "sched responder retry\n");
deviceNeedsRetry = false;
schedule(sendDeviceRetryEvent, nextCycle());
}
diff --git a/src/dev/arm/smmu_v3_slaveifc.hh
b/src/dev/arm/smmu_v3_slaveifc.hh
index b4a5df9..9683c38 100644
--- a/src/dev/arm/smmu_v3_slaveifc.hh
+++ b/src/dev/arm/smmu_v3_slaveifc.hh
@@ -73,8 +73,8 @@
const Cycles mainTLBLat;
SMMUSlavePort *responsePort;
- SMMUATSSlavePort atsSlavePort;
- SMMUATSMasterPort atsMasterPort;
+ SMMUATSSlavePort atsResponsePort;
+ SMMUATSMasterPort atsRequestPort;
// in bytes
const unsigned portWidth;
@@ -93,7 +93,7 @@
std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID];
SMMUSignal dependentReqRemoved;
- // Receiving translation requests from the master device
+ // Receiving translation requests from the requestor device
Tick recvAtomic(PacketPtr pkt);
bool recvTimingReq(PacketPtr pkt);
void schedTimingResp(PacketPtr pkt);
diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index 1b54506..802baf5 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -82,7 +82,7 @@
SMMUProcess(name, _smmu),
ifc(_ifc)
{
- // Decrease number of pending translation slots on the slave interface
+ // Decrease number of pending translation slots on the response
interface
assert(ifc.xlateSlotsRemaining > 0);
ifc.xlateSlotsRemaining--;
@@ -92,12 +92,12 @@
SMMUTranslationProcess::~SMMUTranslationProcess()
{
- // Increase number of pending translation slots on the slave interface
+ // Increase number of pending translation slots on the response
interface
assert(ifc.pendingMemAccesses > 0);
ifc.pendingMemAccesses--;
// If no more SMMU memory accesses are pending,
- // signal SMMU Slave Interface as drained
+ // signal SMMU Response Interface as drained
if (ifc.pendingMemAccesses == 0) {
ifc.signalDrainDone();
}
@@ -147,11 +147,11 @@
request.addr, request.size);
- unsigned numSlaveBeats = request.isWrite ?
+ unsigned numResponderBeats = request.isWrite ?
(request.size + (ifc.portWidth - 1)) / ifc.portWidth : 1;
doSemaphoreDown(yield, ifc.responsePortSem);
- doDelay(yield, Cycles(numSlaveBeats));
+ doDelay(yield, Cycles(numResponderBeats));
doSemaphoreUp(ifc.responsePortSem);
@@ -295,7 +295,7 @@
smmuTLBUpdate(yield, tr);
}
- // Simulate pipelined SMMU->SLAVE INTERFACE link
+ // Simulate pipelined SMMU->RESPONSE INTERFACE link
doSemaphoreDown(yield, smmu.smmuIfcSem);
doDelay(yield, Cycles(1)); // serialize transactions
doSemaphoreUp(smmu.smmuIfcSem);
@@ -353,14 +353,14 @@
if (!e) {
DPRINTF(SMMUv3,
- "SLAVE Interface TLB miss vaddr=%#x sid=%#x ssid=%#x\n",
+ "RESPONSE Interface TLB miss vaddr=%#x sid=%#x ssid=%#x\n",
request.addr, request.sid, request.ssid);
return false;
}
DPRINTF(SMMUv3,
- "SLAVE Interface TLB hit vaddr=%#x amask=%#x sid=%#x ssid=%#x "
+ "RESPONSE Interface TLB hit vaddr=%#x amask=%#x sid=%#x
ssid=%#x "
"paddr=%#x\n", request.addr, e->vaMask, request.sid,
request.ssid, e->pa);
@@ -465,7 +465,7 @@
doSemaphoreDown(yield, ifc.mainTLBSem);
DPRINTF(SMMUv3,
- "SLAVE Interface upd vaddr=%#x amask=%#x paddr=%#x sid=%#x "
+ "RESPONSE Interface upd vaddr=%#x amask=%#x paddr=%#x sid=%#x "
"ssid=%#x\n", e.va, e.vaMask, e.pa, e.sid, e.ssid);
ifc.mainTLB->store(e, alloc);
@@ -1226,13 +1226,13 @@
{
assert(tr.fault == FAULT_NONE);
- unsigned numMasterBeats = request.isWrite ?
+ unsigned numRequestorBeats = request.isWrite ?
(request.size + (smmu.requestPortWidth-1))
/ smmu.requestPortWidth :
1;
doSemaphoreDown(yield, smmu.requestPortSem);
- doDelay(yield, Cycles(numMasterBeats));
+ doDelay(yield, Cycles(numRequestorBeats));
doSemaphoreUp(smmu.requestPortSem);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33530
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If766fcc7b6a06420215e814e9a94bfd33b704a0c
Gerrit-Change-Number: 33530
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-MessageType: newchange
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