Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33550 )
Change subject: arch: Replaced master/slave variables
......................................................................
arch: Replaced master/slave variables
Change-Id: I5c9d0cd19709a7e5034625c2dd42ace3a35b787a
---
M src/arch/generic/BaseTLB.py
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index cca7da6..56e8027 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -33,5 +33,7 @@
abstract = True
cxx_header = "arch/generic/tlb.hh"
# Ports to connect with other TLB levels
- slave = VectorSlavePort("Port closer to the CPU side")
- master = RequestPort("Port closer to memory side")
+ cpu_side = VectorSlavePort("Port closer to the CPU side")
+ slave = DeprecatedParam(cpu_side, '`slave` is now called
`cpu_side`')
+ mem_side = RequestPort("Port closer to memory side")
+ master = DeprecatedParam(mem_side, '`master` is now called
`mem_side`')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5c9d0cd19709a7e5034625c2dd42ace3a35b787a
Gerrit-Change-Number: 33550
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <shpar...@ucdavis.edu>
Gerrit-MessageType: newchange
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