Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/33738 )

Change subject: mips,cpu: Get rid of the IsERET StaticInst flag.
......................................................................

mips,cpu: Get rid of the IsERET StaticInst flag.

This is set by MIPS but doesn't have an accessor in StaticInst, and
isn't used by anything.

Change-Id: Ie28d2df134dcf264bca17c9c66dd32515a240492
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33738
Maintainer: Gabe Black <gabebl...@google.com>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
---
M src/arch/mips/isa/decoder.isa
M src/cpu/StaticInstFlags.py
2 files changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index f62000e..76453b0 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -719,7 +719,7 @@
                         LLFlag = 0;
                         Status = status;
                         SRSCtl = srsCtl;
-                    }}, IsReturn, IsSerializing, IsERET);
+                    }}, IsReturn, IsSerializing);

                     0x1F: deret({{
                         DebugReg debug = Debug;
@@ -732,7 +732,7 @@
                             // Undefined;
                         }
                         Debug = debug;
-                    }}, IsReturn, IsSerializing, IsERET);
+                    }}, IsReturn, IsSerializing);
                 }
                 format CP0TLB {
                     0x01: tlbr({{
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index acaa7bf..b70f919 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -85,7 +85,6 @@
         'IsMemBarrier',     # Is a memory barrier
         'IsWriteBarrier',   # Is a write barrier
         'IsReadBarrier',    # Is a read barrier
-        'IsERET',           # <- Causes the IFU to stall (MIPS ISA)

         'IsNonSpeculative', # Should not be executed speculatively
         'IsQuiesce',        # Is a quiesce instruction

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie28d2df134dcf264bca17c9c66dd32515a240492
Gerrit-Change-Number: 33738
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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