Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33278 )
Change subject: sim: Create a Workload object for SE mode.
......................................................................
sim: Create a Workload object for SE mode.
The workload object is still optional for the sake of compatibility,
even though it probably shouldn't be in the long term. If a simulation
is just a collection of components with nothing in particular running on
it, for instance driven by a traffic generator, should it even have a
System object in the first place?
Change-Id: I8bcda72bdfa3730248226fb62f0bba9a83243d95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33278
Reviewed-by: Matthew Poremba <matthew.pore...@amd.com>
Maintainer: Gabe Black <gabebl...@google.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M configs/dram/low_power_sweep.py
M configs/example/apu_se.py
M configs/example/arm/starter_se.py
M configs/example/hmc_hello.py
M configs/example/se.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M src/sim/SConscript
M src/sim/System.py
M src/sim/Workload.py
A src/sim/se_workload.cc
A src/sim/se_workload.hh
M tests/configs/gpu-ruby.py
M tests/gem5/cpu_tests/run.py
M tests/gem5/m5threads_test_atomic/atomic_system.py
20 files changed, 155 insertions(+), 5 deletions(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/dram/low_power_sweep.py
b/configs/dram/low_power_sweep.py
index 292b0fa..a9f7057 100644
--- a/configs/dram/low_power_sweep.py
+++ b/configs/dram/low_power_sweep.py
@@ -93,6 +93,8 @@
voltage_domain =
VoltageDomain(voltage = '1V'))
+system.workload = SEWorkload()
+
# We are fine with 256 MB memory for now.
mem_range = AddrRange('256MB')
# Start address is 0
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 03418c3..077ce4c 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -500,7 +500,8 @@
system = System(cpu = cpu_list,
mem_ranges = [AddrRange(options.mem_size)],
cache_line_size = options.cacheline_size,
- mem_mode = mem_mode)
+ mem_mode = mem_mode,
+ workload = SEWorkload())
if fast_forward:
system.future_cpu = future_cpu_list
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
diff --git a/configs/example/arm/starter_se.py
b/configs/example/arm/starter_se.py
index 0003ce9..d342420 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -171,6 +171,8 @@
(len(processes), args.num_cores))
sys.exit(1)
+ system.workload = SEWorkload()
+
# Assign one workload to each CPU
for cpu, workload in zip(system.cpu_cluster.cpus, processes):
cpu.workload = workload
diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py
index a682519..706fc2b 100644
--- a/configs/example/hmc_hello.py
+++ b/configs/example/hmc_hello.py
@@ -50,6 +50,7 @@
options = parser.parse_args()
# create the system we are going to simulate
system = System()
+system.workload = SEWorkload()
# use timing mode for the interaction between master-slave ports
system.mem_mode = 'timing'
# set the clock fequency of the system
diff --git a/configs/example/se.py b/configs/example/se.py
index 200a0de..f3fea61 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -173,7 +173,7 @@
mem_mode = test_mem_mode,
mem_ranges = [AddrRange(options.mem_size)],
cache_line_size = options.cacheline_size,
- workload = NULL)
+ workload = SEWorkload())
if numThreads > 1:
system.multi_thread = True
diff --git a/configs/learning_gem5/part1/simple.py
b/configs/learning_gem5/part1/simple.py
index 22b2cf7..cb785b6 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -94,6 +94,8 @@
binary = os.path.join(thispath, '../../../',
'tests/test-progs/hello/bin/', isa, 'linux/hello')
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
diff --git a/configs/learning_gem5/part1/two_level.py
b/configs/learning_gem5/part1/two_level.py
index 53e1137..50d1d5f 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -137,6 +137,8 @@
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
diff --git a/configs/learning_gem5/part2/simple_cache.py
b/configs/learning_gem5/part2/simple_cache.py
index 533aa23..391de8b 100644
--- a/configs/learning_gem5/part2/simple_cache.py
+++ b/configs/learning_gem5/part2/simple_cache.py
@@ -84,6 +84,8 @@
# Connect the system up to the membus
system.system_port = system.membus.slave
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
diff --git a/configs/learning_gem5/part2/simple_memobj.py
b/configs/learning_gem5/part2/simple_memobj.py
index b7d2561..80f6602 100644
--- a/configs/learning_gem5/part2/simple_memobj.py
+++ b/configs/learning_gem5/part2/simple_memobj.py
@@ -82,6 +82,8 @@
# Connect the system up to the membus
system.system_port = system.membus.slave
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
diff --git a/configs/learning_gem5/part3/simple_ruby.py
b/configs/learning_gem5/part3/simple_ruby.py
index 760a168..f0a9e08 100644
--- a/configs/learning_gem5/part3/simple_ruby.py
+++ b/configs/learning_gem5/part3/simple_ruby.py
@@ -89,6 +89,8 @@
binary =
os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/',
isa, 'linux/threads')
+system.workload = SEWorkload()
+
# Create a process for a simple "multi-threaded" application
process = Process()
# Set the command
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index 0e92625..2b36c82 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -216,6 +216,8 @@
system.toL2bus = L2XBar(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
+system.workload = SEWorkload()
+
# ----------------------
# Connect the L2 cache and memory together
# ----------------------
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 7ad2dac..b3b8787 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -195,7 +195,8 @@
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cpus, physmem = SimpleMemory(),
- membus = SystemXBar(clock = busFrequency))
+ membus = SystemXBar(clock = busFrequency),
+ workload = SEWorkload())
system.clock = '1GHz'
system.toL2bus = L2XBar(clock = busFrequency)
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 0bdf921..6bda828 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -63,6 +63,7 @@
Source('root.cc')
Source('serialize.cc')
Source('drain.cc')
+Source('se_workload.cc')
Source('sim_events.cc')
Source('sim_object.cc')
Source('sub_system.cc')
diff --git a/src/sim/System.py b/src/sim/System.py
index caf32fb..a2f6056 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -111,7 +111,7 @@
work_cpus_ckpt_count = Param.Counter(0,
"create checkpoint when active cpu count value is reached")
- workload = Param.Workload(NULL, "Operating system kernel")
+ workload = Param.Workload(NULL, "Workload to run on this system")
init_param = Param.UInt64(0, "numerical value to pass into simulator")
readfile = Param.String("", "file to read startup script from")
symbolfile = Param.String("", "file to get the symbols from")
diff --git a/src/sim/Workload.py b/src/sim/Workload.py
index 1e35abe..f1974bb 100644
--- a/src/sim/Workload.py
+++ b/src/sim/Workload.py
@@ -50,3 +50,7 @@
load_addr_offset = Param.UInt64(0, "Address to offset the kernel with")
command_line = Param.String("a", "boot flags to pass to the kernel")
+
+class SEWorkload(Workload):
+ type = 'SEWorkload'
+ cxx_header = "sim/se_workload.hh"
diff --git a/src/sim/se_workload.cc b/src/sim/se_workload.cc
new file mode 100644
index 0000000..f2a01d5
--- /dev/null
+++ b/src/sim/se_workload.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sim/se_workload.hh"
+
+#include "params/SEWorkload.hh"
+
+SEWorkload::SEWorkload(const Params &p) : Workload(&p), _params(p)
+{
+}
+
+SEWorkload *
+SEWorkloadParams::create()
+{
+ return new SEWorkload(*this);
+}
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
new file mode 100644
index 0000000..b72e824
--- /dev/null
+++ b/src/sim/se_workload.hh
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SIM_SE_WORKLOAD_HH__
+#define __SIM_SE_WORKLOAD_HH__
+
+#include "params/SEWorkload.hh"
+#include "sim/workload.hh"
+
+class SEWorkload : public Workload
+{
+ public:
+ using Params = SEWorkloadParams;
+
+ protected:
+ const Params &_params;
+
+ public:
+ const Params ¶ms() const { return _params; }
+
+ SEWorkload(const Params &p);
+
+ Addr
+ getEntry() const override
+ {
+ // This object represents the OS, not the individual processes
running
+ // within it.
+ panic("No workload entry point for syscall emulation mode.");
+ }
+
+ Loader::Arch
+ getArch() const override
+ {
+ // ISA specific subclasses should implement this method.
+ // This implemenetation is just to avoid having to implement those
for
+ // now, and will be removed in the future.
+ panic("SEWorkload::getArch() not implemented.");
+ }
+
+ const Loader::SymbolTable &
+ symtab(ThreadContext *) override
+ {
+ // This object represents the OS, not the individual processes
running
+ // within it.
+ panic("No workload symbol table for syscall emulation mode.");
+ }
+
+ bool
+ insertSymbol(const Loader::Symbol &symbol) override
+ {
+ // This object represents the OS, not the individual processes
running
+ // within it.
+ panic("No workload symbol table for syscall emulation mode.");
+ }
+};
+
+#endif // __SIM_SE_WORKLOAD_HH__
diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py
index 155775a..a463fe3 100644
--- a/tests/configs/gpu-ruby.py
+++ b/tests/configs/gpu-ruby.py
@@ -261,7 +261,8 @@
system = System(cpu = cpu_list,
mem_ranges = [AddrRange(options.mem_size)],
- mem_mode = 'timing')
+ mem_mode = 'timing',
+ workload = SEWorkload())
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py
index 4d2daf1..b893b80 100644
--- a/tests/gem5/cpu_tests/run.py
+++ b/tests/gem5/cpu_tests/run.py
@@ -119,6 +119,8 @@
system = System()
+system.workload = SEWorkload()
+
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/tests/gem5/m5threads_test_atomic/atomic_system.py
b/tests/gem5/m5threads_test_atomic/atomic_system.py
index 2d9b129..a08be5c 100644
--- a/tests/gem5/m5threads_test_atomic/atomic_system.py
+++ b/tests/gem5/m5threads_test_atomic/atomic_system.py
@@ -40,6 +40,8 @@
root = Root(full_system = False)
root.system = System()
+root.system.workload = SEWorkload()
+
root.system.clk_domain = SrcClockDomain()
root.system.clk_domain.clock = '3GHz'
root.system.clk_domain.voltage_domain = VoltageDomain()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8bcda72bdfa3730248226fb62f0bba9a83243d95
Gerrit-Change-Number: 33278
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Brandon Potter <ambitiousc...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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