Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34795 )
Change subject: arch-arm: TLBI ALLE2IS should broadcast to the IS domain
......................................................................
arch-arm: TLBI ALLE2IS should broadcast to the IS domain
This was implemented as a normal ALLE2 hence affecting the
current PE only
Change-Id: Ib369dd5a4b738daf96a01b5535d7481a97bb3730
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34795
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa.cc
1 file changed, 11 insertions(+), 2 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9ace236..cfef0ab 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1711,9 +1711,8 @@
tlbiOp.broadcast(tc);
return;
}
- // AArch64 TLB Invalidate All, EL2, Inner Shareable
+ // AArch64 TLB Invalidate All, EL2
case MISCREG_TLBI_ALLE2:
- case MISCREG_TLBI_ALLE2IS:
{
assert64();
scr = readMiscReg(MISCREG_SCR);
@@ -1722,6 +1721,16 @@
tlbiOp(tc);
return;
}
+ // AArch64 TLB Invalidate All, EL2, Inner Shareable
+ case MISCREG_TLBI_ALLE2IS:
+ {
+ assert64();
+ scr = readMiscReg(MISCREG_SCR);
+
+ TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
+ tlbiOp.broadcast(tc);
+ return;
+ }
// AArch64 TLB Invalidate All, EL1
case MISCREG_TLBI_ALLE1:
case MISCREG_TLBI_VMALLS12E1:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib369dd5a4b738daf96a01b5535d7481a97bb3730
Gerrit-Change-Number: 34795
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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