Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34978 )
Change subject: arch-arm: Replace any getDTBPtr/getITBPtr usage
......................................................................
arch-arm: Replace any getDTBPtr/getITBPtr usage
The getMMUPtr should be used instead
Change-Id: I8f09b0dc9844764fbe1a04b34dd963730c91f531
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/remote_gdb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_record_v8.cc
M src/arch/arm/utility.cc
7 files changed, 210 insertions(+), 89 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index cfef0ab..f75cc37 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -132,8 +132,7 @@
// Invalidate cached copies of miscregs in the TLBs
if (tc) {
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
}
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
@@ -837,12 +836,11 @@
int old_mode = old_cpsr.mode;
CPSR cpsr = val;
if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
}
if (cpsr.pan != old_cpsr.pan) {
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
}
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d
mode:%#x\n",
@@ -1357,8 +1355,7 @@
}
break;
case MISCREG_SCR:
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
break;
case MISCREG_SCTLR:
{
@@ -1376,8 +1373,7 @@
SCTLR new_sctlr = newVal;
new_sctlr.nmfi = ((bool)sctlr.nmfi)
&& !haveVirtualization;
miscRegs[sctlr_idx] = (RegVal)new_sctlr;
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
}
case MISCREG_MIDR:
case MISCREG_ID_PFR0:
@@ -2080,8 +2076,7 @@
newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
}
// Invalidate TLB MiscReg
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
break;
}
case MISCREG_TTBR0:
@@ -2097,8 +2092,7 @@
}
}
// Invalidate TLB MiscReg
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
break;
}
case MISCREG_SCTLR_EL1:
@@ -2121,15 +2115,13 @@
case MISCREG_TTBR0_EL2:
case MISCREG_TTBR1_EL2:
case MISCREG_TTBR0_EL3:
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
break;
case MISCREG_HCR_EL2:
{
const HDCR mdcr =
tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
selfDebug->setenableTDETGE((HCR)val, mdcr);
- getITBPtr(tc)->invalidateMiscReg();
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg();
}
break;
case MISCREG_NZCV:
@@ -2177,7 +2169,7 @@
case MISCREG_PAN:
{
// PAN is affecting data accesses
- getDTBPtr(tc)->invalidateMiscReg();
+ getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
@@ -2357,13 +2349,13 @@
val, 0, flags, Request::funcRequestorId,
tc->pcState().pc(), tc->contextId());
- Fault fault = getDTBPtr(tc)->translateFunctional(
+ Fault fault = getMMUPtr(tc)->translateFunctional(
req, tc, mode, tran_type);
PAR par = 0;
if (fault == NoFault) {
Addr paddr = req->getPaddr();
- uint64_t attr = getDTBPtr(tc)->getAttr();
+ uint64_t attr = getMMUPtr(tc)->getAttr();
uint64_t attr1 = attr >> 56;
if (!attr1 || attr1 ==0x44) {
attr |= 0x100;
@@ -2408,7 +2400,7 @@
val, 0, flags, Request::funcRequestorId,
tc->pcState().pc(), tc->contextId());
- Fault fault = getDTBPtr(tc)->translateFunctional(
+ Fault fault = getMMUPtr(tc)->translateFunctional(
req, tc, mode, tran_type);
PAR par = 0;
@@ -2427,7 +2419,7 @@
}
par = (paddr & mask(max_paddr_bit, 12)) |
- (getDTBPtr(tc)->getAttr());
+ (getMMUPtr(tc)->getAttr());
DPRINTF(MiscRegs,
"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index b2977e5..bdb018e 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -180,10 +180,9 @@
//
// Calling translateFunctional invokes a table-walk if required
// so we should always succeed
- auto *dtb = tc->getDTBPtr();
- auto *itb = tc->getITBPtr();
- return dtb->translateFunctional(req, tc, BaseTLB::Read) == NoFault ||
- itb->translateFunctional(req, tc, BaseTLB::Read) == NoFault;
+ auto *mmu = tc->getMMUPtr();
+ return mmu->translateFunctional(req, tc, BaseTLB::Read) == NoFault ||
+ mmu->translateFunctional(req, tc, BaseTLB::Execute) == NoFault;
}
RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index dfe09ce..2be6561 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -445,7 +445,7 @@
{
return dynamic_cast<const Params *>(_params);
}
- inline void invalidateMiscReg() { miscRegValid = false; }
+ void invalidateMiscReg() { miscRegValid = false; }
private:
/** Remove any entries that match both a va and asn
@@ -469,26 +469,168 @@
class MMU : public BaseMMU
{
+ protected:
+ ArmISA::TLB *
+ getDTBPtr() const
+ {
+ return static_cast<ArmISA::TLB *>(dtb);
+ }
+
+ ArmISA::TLB *
+ getITBPtr() const
+ {
+ return static_cast<ArmISA::TLB *>(itb);
+ }
+
public:
MMU(const ArmMMUParams *p);
+
+ bool
+ translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
+ {
+ return getDTBPtr()->translateFunctional(tc, vaddr, paddr);
+ }
+
+ Fault
+ translateFunctional(const RequestPtr &req, ThreadContext *tc,
+ BaseTLB::Mode mode, TLB::ArmTranslationType tran_type)
+ {
+ if (mode == BaseTLB::Execute)
+ return getITBPtr()->translateFunctional(req, tc, mode,
tran_type);
+ else
+ return getITBPtr()->translateFunctional(req, tc, mode,
tran_type);
+ }
+
+ void
+ invalidateMiscReg(TLBType type = ALL_TLBS)
+ {
+ if (type & TLBType::I_TLBS) {
+ getITBPtr()->invalidateMiscReg();
+ }
+ if (type & TLBType::D_TLBS) {
+ getDTBPtr()->invalidateMiscReg();
+ }
+ }
+
+ /** Reset the entire TLB
+ * @param secure_lookup if the operation affects the secure world
+ */
+ void
+ flushAllSecurity(bool secure_lookup, ExceptionLevel target_el,
+ TLBType type = ALL_TLBS,
+ bool ignore_el = false, bool in_host = false)
+ {
+ if (type & TLBType::I_TLBS) {
+ getITBPtr()->flushAllSecurity(
+ secure_lookup, target_el, ignore_el, in_host);
+ }
+ if (type & TLBType::D_TLBS) {
+ getDTBPtr()->flushAllSecurity(
+ secure_lookup, target_el, ignore_el, in_host);
+ }
+ }
+
+ /** Remove all entries in the non secure world, depending on whether
they
+ * were allocated in hyp mode or not
+ */
+ void
+ flushAllNs(ExceptionLevel target_el, bool ignore_el = false,
+ TLBType type = ALL_TLBS)
+ {
+ if (type & TLBType::I_TLBS) {
+ getITBPtr()->flushAllNs(target_el, ignore_el);
+ }
+ if (type & TLBType::D_TLBS) {
+ getDTBPtr()->flushAllNs(target_el, ignore_el);
+ }
+ }
+
+ /** Remove any entries that match both a va and asn
+ * @param mva virtual address to flush
+ * @param asn contextid/asn to flush on match
+ * @param secure_lookup if the operation affects the secure world
+ */
+ void
+ flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
+ ExceptionLevel target_el, TLBType type = ALL_TLBS,
+ bool in_host = false)
+ {
+ if (type & TLBType::I_TLBS) {
+ getITBPtr()->flushMvaAsid(
+ mva, asn, secure_lookup, target_el, in_host);
+ }
+ if (type & TLBType::D_TLBS) {
+ getDTBPtr()->flushMvaAsid(
+ mva, asn, secure_lookup, target_el, in_host);
+ }
+ }
+
+ /** Remove any entries that match the asn
+ * @param asn contextid/asn to flush on match
+ * @param secure_lookup if the operation affects the secure world
+ */
+ void
+ flushAsid(uint64_t asn, bool secure_lookup,
+ ExceptionLevel target_el, TLBType type = ALL_TLBS,
+ bool in_host = false)
+ {
+ if (type & TLBType::I_TLBS) {
+ getITBPtr()->flushAsid(asn, secure_lookup, target_el, in_host);
+ }
+ if (type & TLBType::D_TLBS) {
+ getDTBPtr()->flushAsid(asn, secure_lookup, target_el, in_host);
+ }
+ }
+
+ /** Remove all entries that match the va regardless of asn
+ * @param mva address to flush from cache
+ * @param secure_lookup if the operation affects the secure world
+ */
+ void
+ flushMva(Addr mva, bool secure_lookup, ExceptionLevel target_el,
+ TLBType type = ALL_TLBS, bool in_host = false)
+ {
+ if (type & TLBType::I_TLBS) {
+ getITBPtr()->flushMva(mva, secure_lookup, target_el, in_host);
+ }
+ if (type & TLBType::D_TLBS) {
+ getDTBPtr()->flushMva(mva, secure_lookup, target_el, in_host);
+ }
+ }
+
+ /**
+ * Invalidate all entries in the stage 2 TLB that match the given ipa
+ * and the current VMID
+ * @param ipa the address to invalidate
+ * @param secure_lookup if the operation affects the secure world
+ */
+ void
+ flushIpaVmid(Addr ipa, bool secure_lookup, ExceptionLevel target_el,
+ TLBType type = ALL_TLBS)
+ {
+ if (type & TLBType::I_TLBS) {
+ getITBPtr()->flushIpaVmid(ipa, secure_lookup, target_el);
+ }
+ if (type & TLBType::D_TLBS) {
+ getDTBPtr()->flushIpaVmid(ipa, secure_lookup, target_el);
+ }
+ }
+
+ uint64_t
+ getAttr() const
+ {
+ return getDTBPtr()->getAttr();
+ }
+
};
template<typename T>
-TLB *
-getITBPtr(T *tc)
+MMU *
+getMMUPtr(T *tc)
{
- auto tlb = static_cast<TLB *>(tc->getITBPtr());
- assert(tlb);
- return tlb;
-}
-
-template<typename T>
-TLB *
-getDTBPtr(T *tc)
-{
- auto tlb = static_cast<TLB *>(tc->getDTBPtr());
- assert(tlb);
- return tlb;
+ auto mmu = static_cast<MMU *>(tc->getMMUPtr());
+ assert(mmu);
+ return mmu;
}
} // namespace ArmISA
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index f3b9bd1..a249169 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -47,29 +47,27 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
- getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL, in_host);
- getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL, in_host);
+ getMMUPtr(tc)->flushAllSecurity(secureLookup, targetEL,
+ MMU::ALL_TLBS, in_host);
// If CheckerCPU is connected, need to notify it of a flush
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushAllSecurity(secureLookup,
- targetEL, in_host);
- getDTBPtr(checker)->flushAllSecurity(secureLookup,
- targetEL, in_host);
+ getMMUPtr(checker)->flushAllSecurity(
+ secureLookup, targetEL, MMU::ALL_TLBS, in_host);
}
}
void
ITLBIALL::operator()(ThreadContext* tc)
{
- getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
+ getMMUPtr(tc)->flushAllSecurity(secureLookup, targetEL, MMU::I_TLBS);
}
void
DTLBIALL::operator()(ThreadContext* tc)
{
- getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
+ getMMUPtr(tc)->flushAllSecurity(secureLookup, targetEL, MMU::D_TLBS);
}
void
@@ -77,37 +75,35 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
- getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL, in_host);
- getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL, in_host);
+ getMMUPtr(tc)->flushAsid(asid, secureLookup, targetEL,
+ MMU::ALL_TLBS, in_host);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL,
in_host);
- getDTBPtr(checker)->flushAsid(asid, secureLookup, targetEL,
in_host);
+ getMMUPtr(checker)->flushAsid(asid, secureLookup, targetEL,
+ MMU::ALL_TLBS, in_host);
}
}
void
ITLBIASID::operator()(ThreadContext* tc)
{
- getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
+ getMMUPtr(tc)->flushAsid(asid, secureLookup, targetEL, MMU::I_TLBS);
}
void
DTLBIASID::operator()(ThreadContext* tc)
{
- getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
+ getMMUPtr(tc)->flushAsid(asid, secureLookup, targetEL, MMU::D_TLBS);
}
void
TLBIALLN::operator()(ThreadContext* tc)
{
- getITBPtr(tc)->flushAllNs(targetEL);
- getDTBPtr(tc)->flushAllNs(targetEL);
+ getMMUPtr(tc)->flushAllNs(targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushAllNs(targetEL);
- getDTBPtr(checker)->flushAllNs(targetEL);
+ getMMUPtr(checker)->flushAllNs(targetEL);
}
}
@@ -116,13 +112,13 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
- getITBPtr(tc)->flushMva(addr, secureLookup, targetEL, in_host);
- getDTBPtr(tc)->flushMva(addr, secureLookup, targetEL, in_host);
+ getMMUPtr(tc)->flushMva(addr, secureLookup, targetEL,
+ MMU::ALL_TLBS, in_host);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushMva(addr, secureLookup, targetEL,
in_host);
- getDTBPtr(checker)->flushMva(addr, secureLookup, targetEL,
in_host);
+ getMMUPtr(checker)->flushMva(addr, secureLookup, targetEL,
+ MMU::ALL_TLBS, in_host);
}
}
@@ -131,47 +127,39 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool in_host = (hcr.tge == 1 && hcr.e2h == 1);
- getITBPtr(tc)->flushMvaAsid(addr, asid,
- secureLookup, targetEL, in_host);
- getDTBPtr(tc)->flushMvaAsid(addr, asid,
- secureLookup, targetEL, in_host);
+ getMMUPtr(tc)->flushMvaAsid(addr, asid,
+ secureLookup, targetEL, MMU::ALL_TLBS, in_host);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushMvaAsid(
- addr, asid, secureLookup, targetEL, in_host);
- getDTBPtr(checker)->flushMvaAsid(
- addr, asid, secureLookup, targetEL, in_host);
+ getMMUPtr(checker)->flushMvaAsid(
+ addr, asid, secureLookup, targetEL, MMU::ALL_TLBS, in_host);
}
}
void
ITLBIMVA::operator()(ThreadContext* tc)
{
- getITBPtr(tc)->flushMvaAsid(
- addr, asid, secureLookup, targetEL);
+ getMMUPtr(tc)->flushMvaAsid(
+ addr, asid, secureLookup, targetEL, MMU::I_TLBS);
}
void
DTLBIMVA::operator()(ThreadContext* tc)
{
- getDTBPtr(tc)->flushMvaAsid(
- addr, asid, secureLookup, targetEL);
+ getMMUPtr(tc)->flushMvaAsid(
+ addr, asid, secureLookup, targetEL, MMU::D_TLBS);
}
void
TLBIIPA::operator()(ThreadContext* tc)
{
- getITBPtr(tc)->flushIpaVmid(addr,
- secureLookup, targetEL);
- getDTBPtr(tc)->flushIpaVmid(addr,
+ getMMUPtr(tc)->flushIpaVmid(addr,
secureLookup, targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushIpaVmid(addr,
- secureLookup, targetEL);
- getDTBPtr(checker)->flushIpaVmid(addr,
+ getMMUPtr(checker)->flushIpaVmid(addr,
secureLookup, targetEL);
}
}
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index c7bf977..9c2f735 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -1284,13 +1284,13 @@
unsigned flags)
{
const RequestPtr &req = memReq;
- ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
+ auto mmu = static_cast<MMU*>(thread->getMMUPtr());
req->setVirt(addr, size, flags, thread->pcState().instAddr(),
Request::funcRequestorId);
// Translate to physical address
- Fault fault = dtb->translateAtomic(req, thread, BaseTLB::Read);
+ Fault fault = mmu->translateAtomic(req, thread, BaseTLB::Read);
// Ignore read if the address falls into the ignored range
if (parent.ignoredAddrRange.contains(addr))
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc
b/src/arch/arm/tracers/tarmac_record_v8.cc
index fa4304f..29d6492 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -56,8 +56,9 @@
const auto thread = tarmCtx.thread;
// Evaluate physical address
- ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
- paddrValid = dtb->translateFunctional(thread, addr, paddr);
+ auto mmu = static_cast<ArmISA::MMU*>(thread->getMMUPtr());
+ paddrValid = mmu->translateFunctional(
+ thread, addr, paddr);
}
TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8(
@@ -70,8 +71,8 @@
const auto thread = tarmCtx.thread;
// Evaluate physical address
- ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
- dtb->translateFunctional(thread, addr, paddr);
+ auto mmu = static_cast<ArmISA::MMU*>(thread->getMMUPtr());
+ mmu->translateFunctional(thread, addr, paddr);
}
TarmacTracerRecordV8::TraceRegEntryV8::TraceRegEntryV8(
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index a189c4a..156f37f 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -157,8 +157,7 @@
dest->pcState(src->pcState());
// Invalidate the tlb misc register cache
- dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
- dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
+ static_cast<MMU *>(dest->getMMUPtr())->invalidateMiscReg();
}
void
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8f09b0dc9844764fbe1a04b34dd963730c91f531
Gerrit-Change-Number: 34978
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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