Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35076 )
Change subject: arch-arm: arm64 kernel offset into bootloader
......................................................................
arch-arm: arm64 kernel offset into bootloader
This gets Linux 5.8 booting, accounting for its TEXT_OFFSET change
in cfa7ede20f13.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8&id=cfa7ede20f133cc81cef01dc3a516dda3a9721ee
https://lore.kernel.org/r/20200415082922.32709-1-a...@kernel.org
Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
---
M src/dev/arm/RealView.py
M src/sim/kernel_workload.cc
M system/arm/bootloader/arm64/boot.S
M system/arm/bootloader/arm64/makefile
4 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 9ab0472..4768724 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -646,8 +646,11 @@
cpu.append(FdtPropertyStrings('enable-method', 'psci'))
else:
cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
+ # The kernel writes the entry addres of secondary CPUs to this
+ # address before waking up secondary CPUs.
+ # The gem5 bootloader then makes secondary CPUs jump to it.
cpu.append(FdtPropertyWords("cpu-release-addr", \
- state.addrCells(0x8000fff8)))
+ state.addrCells(0x87fffff8)))
class VExpress_EMM(RealView):
_mem_regions = [ AddrRange('2GB', size='2GB') ]
diff --git a/src/sim/kernel_workload.cc b/src/sim/kernel_workload.cc
index d144872..ef3e4ca 100644
--- a/src/sim/kernel_workload.cc
+++ b/src/sim/kernel_workload.cc
@@ -53,8 +53,11 @@
// If load_addr_mask is set to 0x0, then calculate the smallest
mask to
// cover all kernel addresses so gem5 can relocate the kernel to a
new
// offset.
- if (_loadAddrMask == 0)
+ if (_loadAddrMask == 0) {
_loadAddrMask = mask(findMsbSet(_end - _start) + 1);
+ // Make the very first address map exactly to our address
offset.
+ _loadAddrOffset -= (_start & _loadAddrMask);
+ }
image.move([this](Addr a) {
return (a & _loadAddrMask) + _loadAddrOffset;
diff --git a/system/arm/bootloader/arm64/boot.S
b/system/arm/bootloader/arm64/boot.S
index b3baa71..2b3e68f 100644
--- a/system/arm/bootloader/arm64/boot.S
+++ b/system/arm/bootloader/arm64/boot.S
@@ -153,7 +153,19 @@
* Secondary CPUs
*/
1: wfe
- ldr x4, =PHYS_OFFSET + 0xfff8
+ /* The Linux kernel v5.8 and older writes the entry point address
+ * of the secondary CPU to this address, and does a SEV, waking up
+ * the secondary CPUs.
+ *
+ * gem5 informs the kernel the desired address via cpu-release-addr
+ * of the DTB.
+ *
+ * When this is first reached immediately after the bootloader
starts,
+ * the value at that address must be 0, which is the default memory
+ * value set by gem5 for otherwise uninitialized memory, leading to
+ # WFE.
+ */
+ ldr x4, =PHYS_OFFSET + DTB_OFFSET - 8
ldr x4, [x4]
cbz x4, 1b
br x4 // branch to the given address
@@ -180,9 +192,10 @@
/*
* Primary CPU
*/
- ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
- ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
- br x6
+ ldr x0, =PHYS_OFFSET + DTB_OFFSET // device tree blob
+ ldr x6, =PHYS_OFFSET // kernel start address
+ br x6
+ .long 0x80000 // default TEXT_OFFSET
.ltorg
diff --git a/system/arm/bootloader/arm64/makefile
b/system/arm/bootloader/arm64/makefile
index 2112b6e..2c59ea0 100644
--- a/system/arm/bootloader/arm64/makefile
+++ b/system/arm/bootloader/arm64/makefile
@@ -35,6 +35,7 @@
CFLAGS = -march=armv8-a
CPPFLAGS = -DPHYS_OFFSET=0x80000000 \
+ -DDTB_OFFSET=0x8000000 \
-DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 \
-Dkernel=0x80080000 \
-Dmbox=0x8000fff8 -Ddtb=0x80000100
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
Gerrit-Change-Number: 35076
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-MessageType: newchange
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