Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35835 )
Change subject: mem: Add support for PCID to x86
......................................................................
mem: Add support for PCID to x86
This change adds Process Context Identifier (PCID) support
to x86, so that tlb entries can be tagged using pcid.
Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
---
M src/arch/x86/cpuid.cc
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
4 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 64d4544..0210111 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -102,7 +102,7 @@
break;
case FamilyModelSteppingBrandFeatures:
result = CpuidResult(0x00020f51, 0x00000405,
- 0xe3d3fbff, 0x00000001);
+ 0xe3d3fbff, 0x00020001);
break;
case NameString1:
case NameString2:
diff --git a/src/arch/x86/pagetable_walker.cc
b/src/arch/x86/pagetable_walker.cc
index f5b5521..fd9d043 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -549,6 +549,7 @@
{
VAddr addr = vaddr;
CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+ CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
// Check if we're in long mode or not
Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
dataSize = 8;
@@ -560,7 +561,6 @@
enableNX = efer.nxe;
} else {
// We're in some flavor of legacy mode.
- CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
if (cr4.pae) {
// Do legacy PAE.
state = PAEPDP;
@@ -584,7 +584,10 @@
entry.vaddr = vaddr;
Request::Flags flags = Request::PHYSICAL;
- if (cr3.pcd)
+
+ // PCD can't be used if CR4.PCIDE=1 [sec 2.5
+ // of Intel's Software Developer's manual]
+ if (!cr4.pcide && cr3.pcd)
flags.set(Request::UNCACHEABLE);
RequestPtr request = std::make_shared<Request>(
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 7718fdc..2d0439f 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -580,6 +580,17 @@
tc->setMiscReg(MISCREG_CR0, cr0);
tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
+
+ // Setting CR3 to the process pid so that concatinated
+ // page addr with lower 12 bits of CR3 can be used in SE
+ // mode as well to avoid conflicts between tlb entries with
+ // same virtual addresses belonging to different processes
+ tc->setMiscReg(MISCREG_CR3, pTable->pid());
+
+ // Setting pcide bit in CR4
+ CR4 cr4 = 0;
+ cr4.pcide = 1;
+ tc->setMiscReg(MISCREG_CR4, cr4);
}
}
}
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 42b1862..2de38a6 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -616,12 +616,14 @@
// Base Address
Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
// Base Address
+ Bitfield<11, 0> pcid; // Process-Context Identifier
Bitfield<4> pcd; // Page-Level Cache Disable
Bitfield<3> pwt; // Page-Level Writethrough
EndBitUnion(CR3)
BitUnion64(CR4)
Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
+ Bitfield<17> pcide; // PCID Enable
Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
// WRGSBASE instructions
Bitfield<10> osxmmexcpt; // Operating System Unmasked
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Gerrit-Change-Number: 35835
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-MessageType: newchange
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