[gem5-dev] Change in gem5/gem5[develop]: arch-arm: move serialize and unserialize definition to cpp file

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36115 )

Change subject: arch-arm: move serialize and unserialize definition to cpp  
file
......................................................................

arch-arm: move serialize and unserialize definition to cpp file

Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 18 insertions(+), 15 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8ec2dc6..4e90dc8 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2349,6 +2349,22 @@
 }

 void
+ISA::serialize(CheckpointOut &cp) const
+{
+    DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
+    SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+}
+
+void
+ISA::unserialize(CheckpointIn &cp)
+{
+    DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
+    UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+    CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
+    updateRegMap(tmp_cpsr);
+}
+
+void
 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
     BaseTLB::Mode mode, Request::Flags flags, RegVal val)
 {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 910dc2c..43ba8b3 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -810,21 +810,8 @@
         static void zeroSveVecRegUpperPart(VecRegContainer &vc,
                                            unsigned eCount);

-        void
-        serialize(CheckpointOut &cp) const override
-        {
-            DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-            SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-        }
-
-        void
-        unserialize(CheckpointIn &cp) override
-        {
-            DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-            UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-            CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
-            updateRegMap(tmp_cpsr);
-        }
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;

         void startup() override;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Gerrit-Change-Number: 36115
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-MessageType: newchange
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