Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36195 )
Change subject: cpu-o3,stats: Update stats style for cpu.hh and cpu.cc
......................................................................
cpu-o3,stats: Update stats style for cpu.hh and cpu.cc
Change-Id: If4ddaf6a9a84ea71fa19f5ca6d2e5294ec9a0b23
Signed-off-by: Hoa Nguyen <hoangu...@ucdavis.edu>
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
2 files changed, 125 insertions(+), 130 deletions(-)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 368093f..3ce198e 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -127,7 +127,8 @@
globalSeqNum(1),
system(params.system),
- lastRunningCycle(curCycle())
+ lastRunningCycle(curCycle()),
+ cpuStats(this)
{
fatal_if(FullSystem && params.numThreads > 1,
"SMT is not supported in O3 in full system mode currently.");
@@ -384,133 +385,122 @@
}
template <class Impl>
-void
-FullO3CPU<Impl>::regStats()
+FullO3CPU<Impl>::
+FullO3CPUStats::FullO3CPUStats(Stats::Group *parent)
+ : Stats::Group(parent, "FullO3CPU"),
+ ADD_STAT(timesIdled, "Number of times that the entire CPU went into
an "
+ "idle state and unscheduled itself"),
+ ADD_STAT(idleCycles, "Total number of cycles that the CPU has spent "
+ "unscheduled due to idling"),
+ ADD_STAT(quiesceCycles, "Total number of cycles that CPU has spent "
+ "quiesced or waiting for an interrupt"),
+ ADD_STAT(committedInsts, "Number of Instructions Simulated"),
+ ADD_STAT(committedOps, "Number of Ops (including micro ops)
Simulated"),
+ ADD_STAT(cpi, "CPI: Cycles Per Instruction"),
+ ADD_STAT(totalCpi, "CPI: Total CPI of All Threads"),
+ ADD_STAT(ipc, "IPC: Instructions Per Cycle"),
+ ADD_STAT(totalIpc, "IPC: Total IPC of All Threads"),
+ ADD_STAT(intRegfileReads, "Number of integer regfile reads"),
+ ADD_STAT(intRegfileWrites, "Number of integer regfile writes"),
+ ADD_STAT(fpRegfileReads, "Number of floating regfile reads"),
+ ADD_STAT(fpRegfileWrites, "Number of floating regfile writes"),
+ ADD_STAT(vecRegfileReads, "number of vector regfile reads"),
+ ADD_STAT(vecRegfileWrites, "number of vector regfile writes"),
+ ADD_STAT(vecPredRegfileReads, "number of predicate regfile reads"),
+ ADD_STAT(vecPredRegfileWrites, "number of predicate regfile writes"),
+ ADD_STAT(ccRegfileReads, "number of cc regfile reads"),
+ ADD_STAT(ccRegfileWrites, "number of cc regfile writes"),
+ ADD_STAT(miscRegfileReads, "number of misc regfile reads"),
+ ADD_STAT(miscRegfileWrites, "number of misc regfile writes")
{
- BaseO3CPU::regStats();
-
// Register any of the O3CPU's stats here.
timesIdled
- .name(name() + ".timesIdled")
- .desc("Number of times that the entire CPU went into an idle state
and"
- " unscheduled itself")
.prereq(timesIdled);
idleCycles
- .name(name() + ".idleCycles")
- .desc("Total number of cycles that the CPU has spent unscheduled
due "
- "to idling")
.prereq(idleCycles);
quiesceCycles
- .name(name() + ".quiesceCycles")
- .desc("Total number of cycles that CPU has spent quiesced or
waiting "
- "for an interrupt")
.prereq(quiesceCycles);
// Number of Instructions simulated
// --------------------------------
// Should probably be in Base CPU but need templated
// MaxThreads so put in here instead
- committedInsts
- .init(numThreads)
- .name(name() + ".committedInsts")
- .desc("Number of Instructions Simulated")
- .flags(Stats::total);
-
- committedOps
- .init(numThreads)
- .name(name() + ".committedOps")
- .desc("Number of Ops (including micro ops) Simulated")
- .flags(Stats::total);
cpi
- .name(name() + ".cpi")
- .desc("CPI: Cycles Per Instruction")
.precision(6);
- cpi = numCycles / committedInsts;
totalCpi
- .name(name() + ".cpi_total")
- .desc("CPI: Total CPI of All Threads")
.precision(6);
- totalCpi = numCycles / sum(committedInsts);
ipc
- .name(name() + ".ipc")
- .desc("IPC: Instructions Per Cycle")
.precision(6);
- ipc = committedInsts / numCycles;
totalIpc
- .name(name() + ".ipc_total")
- .desc("IPC: Total IPC of All Threads")
.precision(6);
- totalIpc = sum(committedInsts) / numCycles;
-
- this->iew.regStats();
intRegfileReads
- .name(name() + ".int_regfile_reads")
- .desc("number of integer regfile reads")
.prereq(intRegfileReads);
intRegfileWrites
- .name(name() + ".int_regfile_writes")
- .desc("number of integer regfile writes")
.prereq(intRegfileWrites);
fpRegfileReads
- .name(name() + ".fp_regfile_reads")
- .desc("number of floating regfile reads")
.prereq(fpRegfileReads);
fpRegfileWrites
- .name(name() + ".fp_regfile_writes")
- .desc("number of floating regfile writes")
.prereq(fpRegfileWrites);
vecRegfileReads
- .name(name() + ".vec_regfile_reads")
- .desc("number of vector regfile reads")
.prereq(vecRegfileReads);
vecRegfileWrites
- .name(name() + ".vec_regfile_writes")
- .desc("number of vector regfile writes")
.prereq(vecRegfileWrites);
vecPredRegfileReads
- .name(name() + ".pred_regfile_reads")
- .desc("number of predicate regfile reads")
.prereq(vecPredRegfileReads);
vecPredRegfileWrites
- .name(name() + ".pred_regfile_writes")
- .desc("number of predicate regfile writes")
.prereq(vecPredRegfileWrites);
ccRegfileReads
- .name(name() + ".cc_regfile_reads")
- .desc("number of cc regfile reads")
.prereq(ccRegfileReads);
ccRegfileWrites
- .name(name() + ".cc_regfile_writes")
- .desc("number of cc regfile writes")
.prereq(ccRegfileWrites);
miscRegfileReads
- .name(name() + ".misc_regfile_reads")
- .desc("number of misc regfile reads")
.prereq(miscRegfileReads);
miscRegfileWrites
- .name(name() + ".misc_regfile_writes")
- .desc("number of misc regfile writes")
.prereq(miscRegfileWrites);
}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::regStats()
+{
+ BaseO3CPU::regStats();
+
+ cpuStats.committedInsts
+ .init(numThreads)
+ .flags(Stats::total);
+
+ cpuStats.committedOps
+ .init(numThreads)
+ .flags(Stats::total);
+
+ cpuStats.cpi = numCycles / cpuStats.committedInsts;
+ cpuStats.totalCpi = numCycles / sum(cpuStats.committedInsts);
+ cpuStats.ipc = cpuStats.committedInsts / numCycles;
+ cpuStats.totalIpc = sum(cpuStats.committedInsts) / numCycles;
+
+ this->iew.regStats();
+
+}
+
template <class Impl>
void
FullO3CPU<Impl>::tick()
@@ -557,7 +547,7 @@
} else if (!activityRec.active() || _status == Idle) {
DPRINTF(O3CPU, "Idle!\n");
lastRunningCycle = curCycle();
- timesIdled++;
+ cpuStats.timesIdled++;
} else {
schedule(tickEvent, clockEdge(Cycles(1)));
DPRINTF(O3CPU, "Scheduling next tick!\n");
@@ -702,7 +692,7 @@
// @todo: This is an oddity that is only here to match the stats
if (cycles != 0)
--cycles;
- quiesceCycles += cycles;
+ cpuStats.quiesceCycles += cycles;
lastActivatedCycle = curTick();
@@ -1158,7 +1148,7 @@
RegVal
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
- miscRegfileReads++;
+ cpuStats.miscRegfileReads++;
return this->isa[tid]->readMiscReg(misc_reg);
}
@@ -1173,7 +1163,7 @@
void
FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
- miscRegfileWrites++;
+ cpuStats.miscRegfileWrites++;
this->isa[tid]->setMiscReg(misc_reg, val);
}
@@ -1181,7 +1171,7 @@
RegVal
FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
{
- intRegfileReads++;
+ cpuStats.intRegfileReads++;
return regFile.readIntReg(phys_reg);
}
@@ -1189,7 +1179,7 @@
RegVal
FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
{
- fpRegfileReads++;
+ cpuStats.fpRegfileReads++;
return regFile.readFloatReg(phys_reg);
}
@@ -1198,7 +1188,7 @@
FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
-> const VecRegContainer&
{
- vecRegfileReads++;
+ cpuStats.vecRegfileReads++;
return regFile.readVecReg(phys_reg);
}
@@ -1207,7 +1197,7 @@
FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
-> VecRegContainer&
{
- vecRegfileWrites++;
+ cpuStats.vecRegfileWrites++;
return regFile.getWritableVecReg(phys_reg);
}
@@ -1215,7 +1205,7 @@
auto
FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
{
- vecRegfileReads++;
+ cpuStats.vecRegfileReads++;
return regFile.readVecElem(phys_reg);
}
@@ -1224,7 +1214,7 @@
FullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const
-> const VecPredRegContainer&
{
- vecPredRegfileReads++;
+ cpuStats.vecPredRegfileReads++;
return regFile.readVecPredReg(phys_reg);
}
@@ -1233,7 +1223,7 @@
FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
-> VecPredRegContainer&
{
- vecPredRegfileWrites++;
+ cpuStats.vecPredRegfileWrites++;
return regFile.getWritableVecPredReg(phys_reg);
}
@@ -1241,7 +1231,7 @@
RegVal
FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
{
- ccRegfileReads++;
+ cpuStats.ccRegfileReads++;
return regFile.readCCReg(phys_reg);
}
@@ -1249,7 +1239,7 @@
void
FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
{
- intRegfileWrites++;
+ cpuStats.intRegfileWrites++;
regFile.setIntReg(phys_reg, val);
}
@@ -1257,7 +1247,7 @@
void
FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
{
- fpRegfileWrites++;
+ cpuStats.fpRegfileWrites++;
regFile.setFloatReg(phys_reg, val);
}
@@ -1265,7 +1255,7 @@
void
FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer&
val)
{
- vecRegfileWrites++;
+ cpuStats.vecRegfileWrites++;
regFile.setVecReg(phys_reg, val);
}
@@ -1273,7 +1263,7 @@
void
FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
{
- vecRegfileWrites++;
+ cpuStats.vecRegfileWrites++;
regFile.setVecElem(phys_reg, val);
}
@@ -1282,7 +1272,7 @@
FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
const VecPredRegContainer& val)
{
- vecPredRegfileWrites++;
+ cpuStats.vecPredRegfileWrites++;
regFile.setVecPredReg(phys_reg, val);
}
@@ -1290,7 +1280,7 @@
void
FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
- ccRegfileWrites++;
+ cpuStats.ccRegfileWrites++;
regFile.setCCReg(phys_reg, val);
}
@@ -1298,7 +1288,7 @@
RegVal
FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
{
- intRegfileReads++;
+ cpuStats.intRegfileReads++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(IntRegClass, reg_idx));
@@ -1309,7 +1299,7 @@
RegVal
FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
{
- fpRegfileReads++;
+ cpuStats.fpRegfileReads++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(FloatRegClass, reg_idx));
@@ -1370,7 +1360,7 @@
RegVal
FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
{
- ccRegfileReads++;
+ cpuStats.ccRegfileReads++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(CCRegClass, reg_idx));
@@ -1381,7 +1371,7 @@
void
FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
{
- intRegfileWrites++;
+ cpuStats.intRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(IntRegClass, reg_idx));
@@ -1392,7 +1382,7 @@
void
FullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
{
- fpRegfileWrites++;
+ cpuStats.fpRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(FloatRegClass, reg_idx));
@@ -1433,7 +1423,7 @@
void
FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
{
- ccRegfileWrites++;
+ cpuStats.ccRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(CCRegClass, reg_idx));
@@ -1500,7 +1490,7 @@
if (!inst->isMicroop() || inst->isLastMicroop()) {
thread[tid]->numInst++;
thread[tid]->threadStats.numInsts++;
- committedInsts[tid]++;
+ cpuStats.committedInsts[tid]++;
system->totalNumInsts++;
// Check for instruction-count-based events.
@@ -1508,7 +1498,7 @@
}
thread[tid]->numOp++;
thread[tid]->threadStats.numOps++;
- committedOps[tid]++;
+ cpuStats.committedOps[tid]++;
probeInstCommit(inst->staticInst, inst->instAddr());
}
@@ -1691,7 +1681,7 @@
// @todo: This is an oddity that is only here to match the stats
if (cycles > 1) {
--cycles;
- idleCycles += cycles;
+ cpuStats.idleCycles += cycles;
numCycles += cycles;
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index a2735c4..adc7174 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -373,7 +373,7 @@
VecLaneT<VecElem, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
- vecRegfileReads++;
+ cpuStats.vecRegfileReads++;
return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
}
@@ -384,7 +384,7 @@
VecLaneT<VecElem, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
- vecRegfileReads++;
+ cpuStats.vecRegfileReads++;
return regFile.readVecLane<VecElem>(phys_reg);
}
@@ -393,7 +393,7 @@
void
setVecLane(PhysRegIdPtr phys_reg, const LD& val)
{
- vecRegfileWrites++;
+ cpuStats.vecRegfileWrites++;
return regFile.setVecLane(phys_reg, val);
}
@@ -744,44 +744,49 @@
return this->iew.ldstQueue.getDataPort();
}
- /** Stat for total number of times the CPU is descheduled. */
- Stats::Scalar timesIdled;
- /** Stat for total number of cycles the CPU spends descheduled. */
- Stats::Scalar idleCycles;
- /** Stat for total number of cycles the CPU spends descheduled due to a
- * quiesce operation or waiting for an interrupt. */
- Stats::Scalar quiesceCycles;
- /** Stat for the number of committed instructions per thread. */
- Stats::Vector committedInsts;
- /** Stat for the number of committed ops (including micro ops) per
thread. */
- Stats::Vector committedOps;
- /** Stat for the CPI per thread. */
- Stats::Formula cpi;
- /** Stat for the total CPI. */
- Stats::Formula totalCpi;
- /** Stat for the IPC per thread. */
- Stats::Formula ipc;
- /** Stat for the total IPC. */
- Stats::Formula totalIpc;
+ struct FullO3CPUStats : public Stats::Group {
+ FullO3CPUStats(Stats::Group *parent);
- //number of integer register file accesses
- Stats::Scalar intRegfileReads;
- Stats::Scalar intRegfileWrites;
- //number of float register file accesses
- Stats::Scalar fpRegfileReads;
- Stats::Scalar fpRegfileWrites;
- //number of vector register file accesses
- mutable Stats::Scalar vecRegfileReads;
- Stats::Scalar vecRegfileWrites;
- //number of predicate register file accesses
- mutable Stats::Scalar vecPredRegfileReads;
- Stats::Scalar vecPredRegfileWrites;
- //number of CC register file accesses
- Stats::Scalar ccRegfileReads;
- Stats::Scalar ccRegfileWrites;
- //number of misc
- Stats::Scalar miscRegfileReads;
- Stats::Scalar miscRegfileWrites;
+ /** Stat for total number of times the CPU is descheduled. */
+ Stats::Scalar timesIdled;
+ /** Stat for total number of cycles the CPU spends descheduled. */
+ Stats::Scalar idleCycles;
+ /** Stat for total number of cycles the CPU spends descheduled due
to a
+ * quiesce operation or waiting for an interrupt. */
+ Stats::Scalar quiesceCycles;
+ /** Stat for the number of committed instructions per thread. */
+ Stats::Vector committedInsts;
+ /** Stat for the number of committed ops (including micro ops) per
+ * thread. */
+ Stats::Vector committedOps;
+ /** Stat for the CPI per thread. */
+ Stats::Formula cpi;
+ /** Stat for the total CPI. */
+ Stats::Formula totalCpi;
+ /** Stat for the IPC per thread. */
+ Stats::Formula ipc;
+ /** Stat for the total IPC. */
+ Stats::Formula totalIpc;
+
+ //number of integer register file accesses
+ Stats::Scalar intRegfileReads;
+ Stats::Scalar intRegfileWrites;
+ //number of float register file accesses
+ Stats::Scalar fpRegfileReads;
+ Stats::Scalar fpRegfileWrites;
+ //number of vector register file accesses
+ mutable Stats::Scalar vecRegfileReads;
+ Stats::Scalar vecRegfileWrites;
+ //number of predicate register file accesses
+ mutable Stats::Scalar vecPredRegfileReads;
+ Stats::Scalar vecPredRegfileWrites;
+ //number of CC register file accesses
+ Stats::Scalar ccRegfileReads;
+ Stats::Scalar ccRegfileWrites;
+ //number of misc
+ Stats::Scalar miscRegfileReads;
+ Stats::Scalar miscRegfileWrites;
+ } cpuStats;
public:
// hardware transactional memory
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36195
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4ddaf6a9a84ea71fa19f5ca6d2e5294ec9a0b23
Gerrit-Change-Number: 36195
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-MessageType: newchange
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