Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37176 )
Change subject: mem-cache: Add support for interleaved caches.
......................................................................
mem-cache: Add support for interleaved caches.
Add a specialization in the indexing policies and the tag table to allow
for interleaved caches (for example, multibank caches).
The new interleaved set-associative indexing policy makes use of the
address range of the cache, so the `BaseTags` class has a new parameter
with the address range from the parent cache as a default value. The
address manipulation for getting the tag and set or reconstructing the
original address is done with the `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` methods, so this new indexing policy
requires that its cache has one single address range.
Change-Id: I706fa27523b8a33604f18572f0b7e3e88286bbba
Signed-off-by: Isaac Sánchez Barrera <[email protected]>
---
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/indexing_policies/IndexingPolicies.py
M src/mem/cache/tags/indexing_policies/SConscript
A src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
A src/mem/cache/tags/indexing_policies/intlv_set_associative.hh
5 files changed, 231 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index ce086fa..1f0abb1 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -71,6 +71,9 @@
entry_size = Param.Int(Parent.cache_line_size,
"Indexing entry size in bytes")
+ # The addr_ranges of the cache might be needed by some indexing
policies
+ addr_ranges = VectorParam.AddrRange(Parent.addr_ranges, "Address
ranges")
+
class BaseSetAssoc(BaseTags):
type = 'BaseSetAssoc'
cxx_header = "mem/cache/tags/base_set_assoc.hh"
@@ -82,6 +85,9 @@
replacement_policy = Param.BaseReplacementPolicy(
Parent.replacement_policy, "Replacement policy")
+class IntlvSetAssocTags(BaseSetAssoc):
+ indexing_policy = IntlvSetAssociative()
+
class SectorTags(BaseTags):
type = 'SectorTags'
cxx_header = "mem/cache/tags/sector_tags.hh"
diff --git a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
index 7414ddf..237b938 100644
--- a/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
+++ b/src/mem/cache/tags/indexing_policies/IndexingPolicies.py
@@ -51,3 +51,10 @@
type = 'SkewedAssociative'
cxx_class = 'SkewedAssociative'
cxx_header = "mem/cache/tags/indexing_policies/skewed_associative.hh"
+
+class IntlvSetAssociative(SetAssociative):
+ type = 'IntlvSetAssociative'
+ cxx_class = 'IntlvSetAssociative'
+ cxx_header
= "mem/cache/tags/indexing_policies/intlv_set_associative.hh"
+
+ addr_ranges = VectorParam.AddrRange(Parent.addr_ranges, "address
ranges")
diff --git a/src/mem/cache/tags/indexing_policies/SConscript
b/src/mem/cache/tags/indexing_policies/SConscript
index 98c9202..581fd0e 100644
--- a/src/mem/cache/tags/indexing_policies/SConscript
+++ b/src/mem/cache/tags/indexing_policies/SConscript
@@ -30,5 +30,6 @@
SimObject('IndexingPolicies.py')
Source('base.cc')
+Source('intlv_set_associative.cc')
Source('set_associative.cc')
Source('skewed_associative.cc')
diff --git a/src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
b/src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
new file mode 100644
index 0000000..8a0d326
--- /dev/null
+++ b/src/mem/cache/tags/indexing_policies/intlv_set_associative.cc
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2020 Barcelona Supercomputing Center (BSC)
+ * Copyright (c) 2018 Inria
+ * Copyright (c) 2012-2014,2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Definitions of an (interleaved) set associative indexing policy.
+ */
+
+#include "mem/cache/tags/indexing_policies/intlv_set_associative.hh"
+
+#include "mem/cache/replacement_policies/replaceable_entry.hh"
+
+IntlvSetAssociative::IntlvSetAssociative(const Params &p)
+ : SetAssociative(p),
+ addrRange(p.addr_ranges.front())
+{
+ if (p.addr_ranges.size() != 1) {
+ fatal("Got %d ranges, interleaved cache only supports one range\n",
+ p.addr_ranges.size());
+ }
+
+ if (!addrRange.interleaved()) {
+ fatal("In order to use interleaved cache, set ranges
accordingly\n");
+ }
+}
+
+
+uint32_t
+IntlvSetAssociative::extractSet(const Addr addr) const
+{
+ Addr intlv_addr = addrRange.removeIntlvBits(addr);
+ return SetAssociative::extractSet(intlv_addr);
+}
+
+Addr
+IntlvSetAssociative::regenerateAddr(const Addr tag,
+ const ReplaceableEntry* entry) const
+{
+ Addr intlv_addr = SetAssociative::regenerateAddr(tag, entry);
+ return addrRange.addIntlvBits(intlv_addr);
+}
+
+Addr
+IntlvSetAssociative::extractTag(const Addr addr) const
+{
+ Addr intlv_addr = addrRange.removeIntlvBits(addr);
+ return SetAssociative::extractTag(intlv_addr);
+}
diff --git a/src/mem/cache/tags/indexing_policies/intlv_set_associative.hh
b/src/mem/cache/tags/indexing_policies/intlv_set_associative.hh
new file mode 100644
index 0000000..2b8fdeb
--- /dev/null
+++ b/src/mem/cache/tags/indexing_policies/intlv_set_associative.hh
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2020 Barcelona Supercomputing Center (BSC)
+ * Copyright (c) 2018 Inria
+ * Copyright (c) 2012-2014,2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a set associative indexing policy.
+ */
+
+#ifndef __MEM_CACHE_INDEXING_POLICIES_INTLV_SET_ASSOCIATIVE_HH__
+#define __MEM_CACHE_INDEXING_POLICIES_INTLV_SET_ASSOCIATIVE_HH__
+
+#include "mem/cache/tags/indexing_policies/set_associative.hh"
+#include "params/IntlvSetAssociative.hh"
+
+/**
+ * An interleaved set associative indexing policy.
+ * @sa \ref gem5MemorySystem "gem5 Memory System"
+ *
+ * The set associative indexing policy has an immutable/identity mapping,
so a
+ * value x is always mapped to set x, independent of the way, that is,
+ * Hash(A, 0) = Hash(A, 1) = Hash(A, N-1), where N is the number of ways.
+ *
+ * For example, let's assume address A maps to set 3 on way 0. This policy
+ * makes so that A is also mappable to set 3 on every other way. Visually,
the
+ * possible locations of A are, for a table with 4 ways and 8 sets:
+ * Way 0 1 2 3
+ * Set _ _ _ _
+ * 0 |_| |_| |_| |_|
+ * 1 |_| |_| |_| |_|
+ * 2 |_| |_| |_| |_|
+ * 3 |X| |X| |X| |X|
+ * 4 |_| |_| |_| |_|
+ * 5 |_| |_| |_| |_|
+ * 6 |_| |_| |_| |_|
+ * 7 |_| |_| |_| |_|
+ *
+ * In this case, we are considering an interleaved cache, so the bits for
the
+ * interleave need to be taken into account.
+ */
+class IntlvSetAssociative : public SetAssociative
+{
+ protected:
+ /**
+ * The address range defining the interleave policy.
+ */
+ const AddrRange addrRange;
+
+ /**
+ * Apply a hash function to calculate address set.
+ *
+ * @param addr The address to calculate the set for.
+ * @return The set index for given combination of address and way.
+ */
+ uint32_t extractSet(const Addr addr) const override;
+
+ public:
+ /**
+ * Convenience typedef.
+ */
+ typedef IntlvSetAssociativeParams Params;
+
+ /**
+ * Construct and initialize this policy.
+ */
+ IntlvSetAssociative(const Params &p);
+
+ /**
+ * Destructor.
+ */
+ ~IntlvSetAssociative() {};
+
+ /**
+ * Generate the tag from the given address.
+ *
+ * @param addr The address to get the tag from.
+ * @return The tag of the address.
+ */
+ Addr extractTag(const Addr addr) const override;
+
+ /**
+ * Regenerate an entry's address from its tag and assigned indexing
bits.
+ *
+ * @param tag The tag bits.
+ * @param entry The entry.
+ * @return the entry's original address.
+ */
+ Addr regenerateAddr(const Addr tag, const ReplaceableEntry* entry)
const
+
override;
+};
+
+#endif //__MEM_CACHE_INDEXING_POLICIES_INTLV_SET_ASSOCIATIVE_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I706fa27523b8a33604f18572f0b7e3e88286bbba
Gerrit-Change-Number: 37176
Gerrit-PatchSet: 1
Gerrit-Owner: Isaac Sánchez Barrera <[email protected]>
Gerrit-MessageType: newchange
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