[gem5-dev] Change in gem5/gem5[develop]: cpu: Adding connector post Timing access

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37416 )

Change subject: cpu: Adding connector post Timing access
......................................................................

cpu: Adding connector post Timing access

This patch adds a new connector to architecture dependent code
in completeDataAccess. This is used for address based memory
barrier to release the block after that access. The address based
barrier is implemented on architecture dependent code. Its implementation
for ARM arch can be accessed in dependent commits.

Change-Id: I8c75cd77dc6c9f9ae5e416608ce3d8ddb7b2ecf9
---
M src/arch/generic/tlb.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/timing.cc
3 files changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 59b3a01..21d80c1 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -98,6 +98,8 @@
         panic("Not implemented.\n");
     }

+    virtual void handleOrdering(ThreadContext *tc, RequestPtr &req) = 0;
+
     /**
      * Do post-translation physical address finalization.
      *
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index b67edc4..519e288 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -970,6 +970,7 @@
     state->outstanding--;
     assert(pkt == _packets.front());
     _port.completeDataAccess(pkt);
+    _port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),  
pkt->req);
     return true;
 }

@@ -996,6 +997,8 @@
             resp->dataStatic(_data);
         resp->senderState = _senderState;
         _port.completeDataAccess(resp);
+        _port.getMMUPtr()->dtb->handleOrdering(_inst->thread->getTC(),
+                                               pkt->req);
         delete resp;
     }
     return true;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9c529b4..06212c7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1046,8 +1046,10 @@
             panic("HTM - unhandled rc %s", htmFailureToStr(htm_rc));
         }
     } else {
+        SimpleThread* thread = t_info->thread;
         fault = curStaticInst->completeAcc(pkt, t_info,
                                      traceData);
+        thread->mmu->dtb->handleOrdering(thread->getTC(), pkt->req);
     }

     // hardware transactional memory

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8c75cd77dc6c9f9ae5e416608ce3d8ddb7b2ecf9
Gerrit-Change-Number: 37416
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero <jordi.vaqu...@metempsy.com>
Gerrit-MessageType: newchange
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