Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37937 )
Change subject: mem-ruby: Update stats of AbstractController and derived
classes
......................................................................
mem-ruby: Update stats of AbstractController and derived classes
Change-Id: Ia125ef0c3e9112ca7fe709e4a1b2bd343042a52f
Signed-off-by: Hoa Nguyen <hoangu...@ucdavis.edu>
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
3 files changed, 112 insertions(+), 100 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 1e8d8e0..f8eae37 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -56,7 +56,8 @@
m_buffer_size(p.buffer_size), m_recycle_latency(p.recycle_latency),
m_mandatory_queue_latency(p.mandatory_queue_latency),
memoryPort(csprintf("%s.memory", name()), this),
- addrRanges(p.addr_ranges.begin(), p.addr_ranges.end())
+ addrRanges(p.addr_ranges.begin(), p.addr_ranges.end()),
+ stats(this)
{
if (m_version == 0) {
// Combine the statistics from all controllers
@@ -68,11 +69,11 @@
void
AbstractController::init()
{
- m_delayHistogram.init(10);
+ stats.m_delayHistogram.init(10);
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
- m_delayVCHistogram.push_back(new Stats::Histogram());
- m_delayVCHistogram[i]->init(10);
+ stats.m_delayVCHistogram.push_back(new Stats::Histogram(this));
+ stats.m_delayVCHistogram[i]->init(10);
}
if (getMemReqQueue()) {
@@ -106,10 +107,10 @@
void
AbstractController::resetStats()
{
- m_delayHistogram.reset();
+ stats.m_delayHistogram.reset();
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
- m_delayVCHistogram[i]->reset();
+ stats.m_delayVCHistogram[i]->reset();
}
}
@@ -117,19 +118,14 @@
AbstractController::regStats()
{
ClockedObject::regStats();
-
- m_fully_busy_cycles
- .name(name() + ".fully_busy_cycles")
- .desc("cycles for which number of transistions == max transitions")
- .flags(Stats::nozero);
}
void
AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
{
- assert(virtualNetwork < m_delayVCHistogram.size());
- m_delayHistogram.sample(delay);
- m_delayVCHistogram[virtualNetwork]->sample(delay);
+ assert(virtualNetwork < stats.m_delayVCHistogram.size());
+ stats.m_delayHistogram.sample(delay);
+ stats.m_delayVCHistogram[virtualNetwork]->sample(delay);
}
void
@@ -423,3 +419,15 @@
: RequestPort(_name, _controller, id), controller(_controller)
{
}
+
+AbstractController::
+ControllerStats::ControllerStats(Stats::Group *parent)
+ : Stats::Group(parent, "Controller"),
+ m_fully_busy_cycles(this, "fully_busy_cycles",
+ "cycles for which number of transistions == max "
+ "transitions"),
+ m_delayHistogram(this, "delay_histogram")
+{
+ m_fully_busy_cycles
+ .flags(Stats::nozero);
+}
\ No newline at end of file
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 8e19195..7dc2e42 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -151,9 +151,9 @@
MachineID getMachineID() const { return m_machineID; }
RequestorID getRequestorId() const { return m_id; }
- Stats::Histogram& getDelayHist() { return m_delayHistogram; }
+ Stats::Histogram& getDelayHist() { return stats.m_delayHistogram; }
Stats::Histogram& getDelayVCHist(uint32_t index)
- { return *(m_delayVCHistogram[index]); }
+ { return *(stats.m_delayVCHistogram[index]); }
bool respondsTo(Addr addr)
{
@@ -204,14 +204,6 @@
std::unordered_map<Addr, TransMapPair> m_inTrans;
std::unordered_map<Addr, TransMapPair> m_outTrans;
- // Initialized by the SLICC compiler for all combinations of event and
- // states. Only histograms with samples will appear in the stats
- std::vector<std::vector<std::vector<Stats::Histogram*>>>
m_inTransLatHist;
-
- // Initialized by the SLICC compiler for all events.
- // Only histograms with samples will appear in the stats.
- std::vector<Stats::Histogram*> m_outTransLatHist;
-
/**
* Profiles an event that initiates a protocol transactions for a
specific
* line (e.g. events triggered by incoming request messages).
@@ -241,7 +233,7 @@
{
auto iter = m_inTrans.find(addr);
assert(iter != m_inTrans.end());
- m_inTransLatHist[iter->second.transaction]
+ stats.m_inTransLatHist[iter->second.transaction]
[iter->second.state]
[(unsigned)finalState]->sample(
ticksToCycles(curTick() - iter->second.time));
@@ -272,7 +264,7 @@
{
auto iter = m_outTrans.find(addr);
assert(iter != m_outTrans.end());
- m_outTransLatHist[iter->second.transaction]->sample(
+ stats.m_outTransLatHist[iter->second.transaction]->sample(
ticksToCycles(curTick() - iter->second.time));
m_outTrans.erase(iter);
}
@@ -308,15 +300,6 @@
Cycles m_recycle_latency;
const Cycles m_mandatory_queue_latency;
- //! Counter for the number of cycles when the transitions carried out
- //! were equal to the maximum allowed
- Stats::Scalar m_fully_busy_cycles;
-
- //! Histogram for profiling delay for the messages this controller
- //! cares for
- Stats::Histogram m_delayHistogram;
- std::vector<Stats::Histogram *> m_delayVCHistogram;
-
/**
* Port that forwards requests and receives responses from the
* memory controller.
@@ -363,6 +346,30 @@
NetDest downstreamDestinations;
+
+ public:
+ struct ControllerStats : public Stats::Group
+ {
+ ControllerStats(Stats::Group *parent);
+
+ // Initialized by the SLICC compiler for all combinations of event
and
+ // states. Only histograms with samples will appear in the stats
+ std::vector<std::vector<std::vector<Stats::Histogram*>>>
+ m_inTransLatHist;
+
+ // Initialized by the SLICC compiler for all events.
+ // Only histograms with samples will appear in the stats.
+ std::vector<Stats::Histogram*> m_outTransLatHist;
+
+ //! Counter for the number of cycles when the transitions carried
out
+ //! were equal to the maximum allowed
+ Stats::Scalar m_fully_busy_cycles;
+
+ //! Histogram for profiling delay for the messages this controller
+ //! cares for
+ Stats::Histogram m_delayHistogram;
+ std::vector<Stats::Histogram *> m_delayVCHistogram;
+ } stats;
};
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index c4601bb..701075a 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -599,6 +599,67 @@
''')
code.dedent()
code('''
+ // initialize stats
+ if (m_version == 0) {
+ for (${ident}_Event event = ${ident}_Event_FIRST;
+ event < ${ident}_Event_NUM; ++event) {
+ Stats::Vector *t = new Stats::Vector(&stats);
+ t->init(m_num_controllers);
+ t->name("${c_ident}." + ${ident}_Event_to_string(event));
+ t->flags(Stats::pdf | Stats::total | Stats::oneline |
+ Stats::nozero);
+
+ eventVec.push_back(t);
+ }
+
+ for (${ident}_State state = ${ident}_State_FIRST;
+ state < ${ident}_State_NUM; ++state) {
+
+ transVec.push_back(std::vector<Stats::Vector *>());
+
+ for (${ident}_Event event = ${ident}_Event_FIRST;
+ event < ${ident}_Event_NUM; ++event) {
+
+ Stats::Vector *t = new Stats::Vector(&stats);
+ t->init(m_num_controllers);
+ t->name("${c_ident}." + ${ident}_State_to_string(state) +
+ "." + ${ident}_Event_to_string(event));
+
+ t->flags(Stats::pdf | Stats::total | Stats::oneline |
+ Stats::nozero);
+ transVec[state].push_back(t);
+ }
+ }
+ }
+ for (${ident}_Event event = ${ident}_Event_FIRST;
+ event < ${ident}_Event_NUM; ++event) {
+ Stats::Histogram* t = new Stats::Histogram(&stats);
+ stats.m_outTransLatHist.push_back(t);
+ t->init(5);
+ t->name("${ident}.outTransLatHist." +
${ident}_Event_to_string(event));
+ t->flags(Stats::pdf | Stats::total |
+ Stats::oneline | Stats::nozero);
+ }
+ for (${ident}_Event event = ${ident}_Event_FIRST;
+ event < ${ident}_Event_NUM; ++event) {
+ stats.m_inTransLatHist.emplace_back();
+ for (${ident}_State initial_state = ${ident}_State_FIRST;
+ initial_state < ${ident}_State_NUM; ++initial_state) {
+ stats.m_inTransLatHist.back().emplace_back();
+ for (${ident}_State final_state = ${ident}_State_FIRST;
+ final_state < ${ident}_State_NUM; ++final_state) {
+ Stats::Histogram* t = new Stats::Histogram(&stats);
+ stats.m_inTransLatHist.back().back().push_back(t);
+ t->init(5);
+ t->name("${ident}.inTransLatHist." +
+ ${ident}_Event_to_string(event) + "." +
+ ${ident}_State_to_string(initial_state) + "." +
+ ${ident}_State_to_string(final_state));
+ t->flags(Stats::pdf | Stats::total |
+ Stats::oneline | Stats::nozero);
+ }
+ }
+ }
}
void
@@ -814,70 +875,6 @@
$c_ident::regStats()
{
AbstractController::regStats();
-
- if (m_version == 0) {
- for (${ident}_Event event = ${ident}_Event_FIRST;
- event < ${ident}_Event_NUM; ++event) {
- Stats::Vector *t = new Stats::Vector();
- t->init(m_num_controllers);
- t->name(params().ruby_system->name() + ".${c_ident}." +
- ${ident}_Event_to_string(event));
- t->flags(Stats::pdf | Stats::total | Stats::oneline |
- Stats::nozero);
-
- eventVec.push_back(t);
- }
-
- for (${ident}_State state = ${ident}_State_FIRST;
- state < ${ident}_State_NUM; ++state) {
-
- transVec.push_back(std::vector<Stats::Vector *>());
-
- for (${ident}_Event event = ${ident}_Event_FIRST;
- event < ${ident}_Event_NUM; ++event) {
-
- Stats::Vector *t = new Stats::Vector();
- t->init(m_num_controllers);
- t->name(params().ruby_system->name() + ".${c_ident}." +
- ${ident}_State_to_string(state) +
- "." + ${ident}_Event_to_string(event));
-
- t->flags(Stats::pdf | Stats::total | Stats::oneline |
- Stats::nozero);
- transVec[state].push_back(t);
- }
- }
- }
- for (${ident}_Event event = ${ident}_Event_FIRST;
- event < ${ident}_Event_NUM; ++event) {
- Stats::Histogram* t = new Stats::Histogram;
- m_outTransLatHist.push_back(t);
- t->init(5);
- t->name(name() + ".outTransLatHist." +
- ${ident}_Event_to_string(event));
- t->flags(Stats::pdf | Stats::total |
- Stats::oneline | Stats::nozero);
- }
- for (${ident}_Event event = ${ident}_Event_FIRST;
- event < ${ident}_Event_NUM; ++event) {
- m_inTransLatHist.emplace_back();
- for (${ident}_State initial_state = ${ident}_State_FIRST;
- initial_state < ${ident}_State_NUM; ++initial_state) {
- m_inTransLatHist.back().emplace_back();
- for (${ident}_State final_state = ${ident}_State_FIRST;
- final_state < ${ident}_State_NUM; ++final_state) {
- Stats::Histogram* t = new Stats::Histogram;
- m_inTransLatHist.back().back().push_back(t);
- t->init(5);
- t->name(name() + ".inTransLatHist." +
- ${ident}_Event_to_string(event) + "." +
- ${ident}_State_to_string(initial_state) + "." +
- ${ident}_State_to_string(final_state));
- t->flags(Stats::pdf | Stats::total |
- Stats::oneline | Stats::nozero);
- }
- }
- }
}
void
@@ -1231,7 +1228,7 @@
assert(counter <= m_transitions_per_cycle);
if (counter == m_transitions_per_cycle) {
// Count how often we are fully utilized
- m_fully_busy_cycles++;
+ stats.m_fully_busy_cycles++;
// Wakeup in another cycle and try again
scheduleEvent(Cycles(1));
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37937
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia125ef0c3e9112ca7fe709e4a1b2bd343042a52f
Gerrit-Change-Number: 37937
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
