Daniel Gerzhoy has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37676 )
Change subject: cpu-o3: Fixed halt assertion failure
......................................................................
cpu-o3: Fixed halt assertion failure
Halting the O3 CPU would cause an assertion failure because
instructions were not finished being squashed in the ROB.
Change-Id: I8b8c375d0e520861af3657249de987de2451b6f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37676
Reviewed-by: Jason Lowe-Power <[email protected]>
Reviewed-by: Bobby R. Bruce <[email protected]>
Maintainer: Bobby R. Bruce <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/rob_impl.hh
2 files changed, 29 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c910cc4..4068b30 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -717,6 +717,15 @@
deactivateThread(tid);
removeThread(tid);
+ // If this was the last thread then unschedule the tick event.
+ if (activeThreads.size() == 0) {
+ if (tickEvent.scheduled())
+ {
+ unscheduleTickEvent();
+ }
+ lastRunningCycle = curCycle();
+ _status = Idle;
+ }
updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
}
@@ -795,6 +804,15 @@
rename.clearStates(tid);
iew.clearStates(tid);
+ // Flush out any old data from the time buffers.
+ for (int i = 0; i < timeBuffer.getSize(); ++i) {
+ timeBuffer.advance();
+ fetchQueue.advance();
+ decodeQueue.advance();
+ renameQueue.advance();
+ iewQueue.advance();
+ }
+
// at this step, all instructions in the pipeline should be already
// either committed successfully or squashed. All thread-specific
// queues in the pipeline must be empty.
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index d4a02b5..73c8a4b 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -338,8 +338,18 @@
bool robTailUpdate = false;
+ unsigned int numInstsToSquash = squashWidth;
+
+ // If the CPU is exiting, squash all of the instructions
+ // it is told to, even if that exceeds the squashWidth.
+ // Set the number to the number of entries (the max).
+ if (cpu->isThreadExiting(tid))
+ {
+ numInstsToSquash = numEntries;
+ }
+
for (int numSquashed = 0;
- numSquashed < squashWidth &&
+ numSquashed < numInstsToSquash &&
squashIt[tid] != instList[tid].end() &&
(*squashIt[tid])->seqNum > squashedSeqNum[tid];
++numSquashed)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8b8c375d0e520861af3657249de987de2451b6f1
Gerrit-Change-Number: 37676
Gerrit-PatchSet: 3
Gerrit-Owner: Daniel Gerzhoy <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Daniel Gerzhoy <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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