Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39955 )
Change subject: arch-riscv: Moving ExceptionCode to registers.hh for
reusability
......................................................................
arch-riscv: Moving ExceptionCode to registers.hh for reusability
The ExceptionCode enum was originally defined in faults.hh. However,
it can actually be reused in registers.hh were interrupt bit locations
were previously hardcoded. I hence suggest moving the ExceptionCode
enum definition to registers.hh and have made the replacements for
the bit locations.
Change-Id: I9475f362b98b2a438786b39f6c0da4fb0e68aa02
---
M src/arch/riscv/faults.hh
M src/arch/riscv/registers.hh
2 files changed, 61 insertions(+), 58 deletions(-)
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 5e24da2..a078662 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -49,46 +49,6 @@
FloatInvalid = 0x10
};
-/*
- * In RISC-V, exception and interrupt codes share some values. They can be
- * differentiated by an 'Interrupt' flag that is enabled for interrupt
faults
- * but not exceptions. The full fault cause can be computed by placing the
- * exception (or interrupt) code in the least significant bits of the CAUSE
- * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
- * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
- * privileged specification v 1.10. Codes are enumerated in Table 3.6.
- */
-enum ExceptionCode : uint64_t {
- INST_ADDR_MISALIGNED = 0,
- INST_ACCESS = 1,
- INST_ILLEGAL = 2,
- BREAKPOINT = 3,
- LOAD_ADDR_MISALIGNED = 4,
- LOAD_ACCESS = 5,
- STORE_ADDR_MISALIGNED = 6,
- AMO_ADDR_MISALIGNED = 6,
- STORE_ACCESS = 7,
- AMO_ACCESS = 7,
- ECALL_USER = 8,
- ECALL_SUPER = 9,
- ECALL_MACHINE = 11,
- INST_PAGE = 12,
- LOAD_PAGE = 13,
- STORE_PAGE = 15,
- AMO_PAGE = 15,
-
- INT_SOFTWARE_USER = 0,
- INT_SOFTWARE_SUPER = 1,
- INT_SOFTWARE_MACHINE = 3,
- INT_TIMER_USER = 4,
- INT_TIMER_SUPER = 5,
- INT_TIMER_MACHINE = 7,
- INT_EXT_USER = 8,
- INT_EXT_SUPER = 9,
- INT_EXT_MACHINE = 11,
- NumInterruptTypes
-};
-
class RiscvFault : public FaultBase
{
protected:
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 9721635..2ba5d2c 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,8 +93,11 @@
const int ZeroReg = 0;
const int ReturnAddrReg = 1;
const int StackPointerReg = 2;
+const int GlobalPointerReg = 3;
const int ThreadPointerReg = 4;
+const int FramePointerReg = 8;
const int ReturnValueReg = 10;
+const std::vector<int> ReturnValueRegs = {10, 11};
const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
const int AMOTempReg = 32;
@@ -616,6 +619,46 @@
Bitfield<0> uie;
EndBitUnion(STATUS)
+/*
+ * In RISC-V, exception and interrupt codes share some values. They can be
+ * differentiated by an 'Interrupt' flag that is enabled for interrupt
faults
+ * but not exceptions. The full fault cause can be computed by placing the
+ * exception (or interrupt) code in the least significant bits of the CAUSE
+ * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
+ * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
+ * privileged specification v 1.10. Codes are enumerated in Table 3.6.
+ */
+enum ExceptionCode : uint64_t {
+ INST_ADDR_MISALIGNED = 0,
+ INST_ACCESS = 1,
+ INST_ILLEGAL = 2,
+ BREAKPOINT = 3,
+ LOAD_ADDR_MISALIGNED = 4,
+ LOAD_ACCESS = 5,
+ STORE_ADDR_MISALIGNED = 6,
+ AMO_ADDR_MISALIGNED = 6,
+ STORE_ACCESS = 7,
+ AMO_ACCESS = 7,
+ ECALL_USER = 8,
+ ECALL_SUPER = 9,
+ ECALL_MACHINE = 11,
+ INST_PAGE = 12,
+ LOAD_PAGE = 13,
+ STORE_PAGE = 15,
+ AMO_PAGE = 15,
+
+ INT_SOFTWARE_USER = 0,
+ INT_SOFTWARE_SUPER = 1,
+ INT_SOFTWARE_MACHINE = 3,
+ INT_TIMER_USER = 4,
+ INT_TIMER_SUPER = 5,
+ INT_TIMER_MACHINE = 7,
+ INT_EXT_USER = 8,
+ INT_EXT_SUPER = 9,
+ INT_EXT_MACHINE = 11,
+ NumInterruptTypes
+};
+
/**
* These fields are specified in the RISC-V Instruction Set Manual, Volume
II,
* v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the
MIP
@@ -623,15 +666,15 @@
* this bit union.
*/
BitUnion64(INTERRUPT)
- Bitfield<11> mei;
- Bitfield<9> sei;
- Bitfield<8> uei;
- Bitfield<7> mti;
- Bitfield<5> sti;
- Bitfield<4> uti;
- Bitfield<3> msi;
- Bitfield<1> ssi;
- Bitfield<0> usi;
+ Bitfield<ExceptionCode::INT_EXT_MACHINE> mei;
+ Bitfield<ExceptionCode::INT_EXT_SUPER> sei;
+ Bitfield<ExceptionCode::INT_EXT_USER> uei;
+ Bitfield<ExceptionCode::INT_TIMER_MACHINE> mti;
+ Bitfield<ExceptionCode::INT_TIMER_SUPER> sti;
+ Bitfield<ExceptionCode::INT_TIMER_USER> uti;
+ Bitfield<ExceptionCode::INT_SOFTWARE_MACHINE> msi;
+ Bitfield<ExceptionCode::INT_SOFTWARE_SUPER> ssi;
+ Bitfield<ExceptionCode::INT_SOFTWARE_USER> usi;
EndBitUnion(INTERRUPT)
const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
@@ -685,15 +728,15 @@
STATUS_FS_MASK | STATUS_UPIE_MASK |
STATUS_UIE_MASK;
-const RegVal MEI_MASK = 1ULL << 11;
-const RegVal SEI_MASK = 1ULL << 9;
-const RegVal UEI_MASK = 1ULL << 8;
-const RegVal MTI_MASK = 1ULL << 7;
-const RegVal STI_MASK = 1ULL << 5;
-const RegVal UTI_MASK = 1ULL << 4;
-const RegVal MSI_MASK = 1ULL << 3;
-const RegVal SSI_MASK = 1ULL << 1;
-const RegVal USI_MASK = 1ULL << 0;
+const RegVal MEI_MASK = 1ULL << ExceptionCode::INT_EXT_MACHINE;
+const RegVal SEI_MASK = 1ULL << ExceptionCode::INT_EXT_SUPER;
+const RegVal UEI_MASK = 1ULL << ExceptionCode::INT_EXT_USER;
+const RegVal MTI_MASK = 1ULL << ExceptionCode::INT_TIMER_MACHINE;
+const RegVal STI_MASK = 1ULL << ExceptionCode::INT_TIMER_SUPER;
+const RegVal UTI_MASK = 1ULL << ExceptionCode::INT_TIMER_USER;
+const RegVal MSI_MASK = 1ULL << ExceptionCode::INT_SOFTWARE_MACHINE;
+const RegVal SSI_MASK = 1ULL << ExceptionCode::INT_SOFTWARE_SUPER;
+const RegVal USI_MASK = 1ULL << ExceptionCode::INT_SOFTWARE_USER;
const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
MTI_MASK | STI_MASK | UTI_MASK |
MSI_MASK | SSI_MASK | USI_MASK;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39955
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9475f362b98b2a438786b39f6c0da4fb0e68aa02
Gerrit-Change-Number: 39955
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen <petery....@huawei.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
