Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40278 )
Change subject: fastmodel: add interface to update system counter freq
......................................................................
fastmodel: add interface to update system counter freq
This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.
Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/iris/cpu.hh
9 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index 0b0fa8d..bbfe18a 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -340,6 +340,7 @@
"signal).")
ptw_latency = Param.UInt64(0, "Page table walker latency for TA "\
"(Timing Annotation), expressed in simulation ticks")
+ sys_counter_frq = Param.UInt64(0x1800000, "The system counter
frequency")
tlb_latency = Param.UInt64(0, "TLB latency for TA (Timing
Annotation), "\
"expressed in simulation ticks")
treat_dcache_cmos_to_pou_as_nop = Param.Bool(False, "Whether dcache "\
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 897be24..7fdc6c2 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -39,8 +39,12 @@
void
CortexA76::initState()
{
+ warn_if(params().cntfrq != cluster->params().sys_counter_frq,
+ "CNTFRQ configured freq does not match the system counter
freq\n");
for (auto *tc : threadContexts)
tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,
params().cntfrq);
+
+ evs_base_cpu->setSysCounterFrq(cluster->params().sys_counter_frq);
}
void
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index b4153cc..c1fe23a 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -46,6 +46,13 @@
template <class Types>
void
+ScxEvsCortexA76<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+ periphClockRateControl->set_mul_div(sys_counter_frq, 1);
+}
+
+template <class Types>
+void
ScxEvsCortexA76<Types>::setCluster(SimObject* cluster)
{
gem5CpuCluster = dynamic_cast<CortexA76Cluster*>(cluster);
@@ -86,6 +93,7 @@
}
clockRateControl.bind(this->clock_rate_s);
+ periphClockRateControl.bind(this->periph_clock_rate_s);
}
template <class Types>
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index 64d605a..c8e20fd 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -63,6 +63,7 @@
SC_HAS_PROCESS(ScxEvsCortexA76);
ClockRateControlInitiatorSocket clockRateControl;
+ ClockRateControlInitiatorSocket periphClockRateControl;
typedef sc_gem5::TlmTargetBaseWrapper<
64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@
void setClkFrq(uint64_t clk_frq) override;
+ void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
void setCluster(SimObject* cluster) override;
};
diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
index 1968931..04dae41 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[1];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index e0f7a93..0279140 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[2];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
index 9ce9027..b18b102 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[3];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
index e4b79ce..c7f1cb2 100644
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
@@ -35,7 +35,7 @@
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
- clockDivPeriph : ClockDivider(mul=0x01800000);
+ clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@
clockDiv.rate.set64(mul, div);
}
}
+ slave port<ExportedClockRateControl> periph_clock_rate_s
+ {
+ behavior set_mul_div(uint64_t mul, uint64_t div)
+ {
+ clockDivPeriph.rate.set64(mul, div);
+ }
+ }
slave port<GICv3Comms> redistributor[4];
// External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh
b/src/arch/arm/fastmodel/iris/cpu.hh
index 812976a..886daaf 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -44,6 +44,7 @@
public:
virtual void sendFunc(PacketPtr pkt) = 0;
virtual void setClkFrq(uint64_t clk_frq) = 0;
+ virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
virtual void setCluster(SimObject* cluster) = 0;
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40278
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
Gerrit-Change-Number: 40278
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou <shunhsin...@google.com>
Gerrit-MessageType: newchange
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