Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40884 )
Change subject: arch-power: Add and rename some opcode fields
......................................................................
arch-power: Add and rename some opcode fields
This introduces separate extended opcode (XO) fields for DS,
X, XFL, XFX, XL and XO form instructions and renames the
primary opcode field to PO based on the convention used in
the Power ISA manual.
Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/unimp.isa
M src/arch/power/isa/formats/unknown.isa
4 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 6cc67dd..3ea6d8c 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -34,10 +34,14 @@
// are reversed sometimes. Not sure of a fix to this though...
// Opcode fields
-def bitfield OPCODE <31:26>;
-def bitfield X_XO <10:0>;
-def bitfield XO_XO <10:1>;
+def bitfield PO <31:26>;
def bitfield A_XO <5:1>;
+def bitfield DS_XO <1:0>;
+def bitfield X_XO <10:1>;
+def bitfield XFL_XO <10:1>;
+def bitfield XFX_XO <10:1>;
+def bitfield XL_XO <10:1>;
+def bitfield XO_XO <9:1>;
// Register fields
def bitfield RA <20:16>;
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 0cf1199..fa6c9cb 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -34,7 +34,7 @@
// I've used the Power ISA Book I v2.06 for instruction formats,
// opcode numbers, register names, etc.
//
-decode OPCODE default Unknown::unknown() {
+decode PO default Unknown::unknown() {
18: decode AA {
diff --git a/src/arch/power/isa/formats/unimp.isa
b/src/arch/power/isa/formats/unimp.isa
index fef28ce..a3f4692 100644
--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -112,7 +112,7 @@
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
- "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst,
OPCODE,
+ "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst,
PO,
inst2string(machInst));
return std::make_shared<UnimplementedOpcodeFault>();
}
diff --git a/src/arch/power/isa/formats/unknown.isa
b/src/arch/power/isa/formats/unknown.isa
index d0f81f1..d83f79c 100644
--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -63,7 +63,7 @@
Addr pc, const Loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
- "unknown", machInst, OPCODE,
inst2string(machInst));
+ "unknown", machInst, PO, inst2string(machInst));
}
}};
@@ -73,7 +73,7 @@
{
panic("attempt to execute unknown instruction at %#x"
"(inst 0x%08x, opcode 0x%x, binary: %s)",
- xc->pcState().pc(), machInst, OPCODE, inst2string(machInst));
+ xc->pcState().pc(), machInst, PO, inst2string(machInst));
return std::make_shared<UnimplementedOpcodeFault>();
}
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Gerrit-Change-Number: 40884
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-MessageType: newchange
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