Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40936 )
Change subject: arch-power: Add move condition field instructions
......................................................................
arch-power: Add move condition field instructions
This adds the following instructions.
* Move to CR from XER Extended (mcrxrx)
* Move To One Condition Register Field (mtocrf)
* Move From One Condition Register Field (mfocrf)
Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
---
M src/arch/power/isa/decoder.isa
1 file changed, 26 insertions(+), 0 deletions(-)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 7f79d3c..4ecee98 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -720,6 +720,16 @@
68: td({{ Ra }}, {{ Rb }});
}
+ format IntOp {
+ 576: mcrxrx({{
+ uint8_t res;
+ Xer xer = XER;
+ res = (xer.ov << 3) | (xer.ov32 << 2) |
+ (xer.ca << 1) | xer.ca32;
+ CR = insertCRField(CR, BF, res);
+ }});
+ }
+
format StoreIndexOp {
663: stfsx({{ Mem_sf = Fs_sf; }});
727: stfdx({{ Mem_df = Fs; }});
@@ -982,10 +992,26 @@
}
CR = (Rs & mask) | (CR & ~mask);
}});
+
+ 1: mtocrf({{
+ int count = popCount(FXM);
+ uint32_t mask = 0xf << (4 *
findMsbSet(FXM));
+ if (count == 1) {
+ CR = (Rs & mask) | (CR & ~mask);
+ }
+ }});
}
19: decode S {
0: mfcr({{ Rt = CR; }});
+
+ 1: mfocrf({{
+ int count = popCount(FXM);
+ uint64_t mask = 0xf << (4 *
findMsbSet(FXM));
+ if (count == 1) {
+ Rt = CR & mask;
+ }
+ }});
}
512: mcrxr({{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Gerrit-Change-Number: 40936
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-MessageType: newchange
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