Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41033 )
Change subject: arch-riscv: FS Linux config file for RISC-V
......................................................................
arch-riscv: FS Linux config file for RISC-V
This file is added to provide a clean starter for RISC-V FS Linux
configuration.
Change-Id: Ifd401761be86758340f26edd00a5ab1ca51e6938
---
A configs/example/riscv/fs_linux.py
1 file changed, 228 insertions(+), 0 deletions(-)
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
new file mode 100644
index 0000000..75c54a5
--- /dev/null
+++ b/configs/example/riscv/fs_linux.py
@@ -0,0 +1,228 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
+# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import optparse
+import sys
+
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+from m5.util import addToPath, fatal, warn
+from m5.util.fdthelper import *
+
+addToPath('../../')
+
+from ruby import Ruby
+
+from common.FSConfig import *
+from common.SysPaths import *
+from common.Benchmarks import *
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import MemConfig
+from common import ObjectList
+from common.Caches import *
+from common import Options
+
+# ----------------------------- Add Options ---------------------------- #
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+Options.addFSOptions(parser)
+
+# NOTE: Ruby in FS Linux has not been tested yet
+if '--ruby' in sys.argv:
+ Ruby.define_options(parser)
+
+# ---------------------------- Parse Options --------------------------- #
+(options, args) = parser.parse_args()
+
+if args:
+ print("Error: script doesn't take any positional arguments")
+ sys.exit(1)
+
+# CPU and Memory
+(CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(options)
+MemClass = Simulation.setMemClass(options)
+
+np = options.num_cpus
+
+# ---------------------------- Setup System ---------------------------- #
+# Edit this section to customize peripherals and system settings
+system = System()
+mdesc = SysConfig(disks=options.disk_image, rootdev=options.root_device,
+ mem=options.mem_size, os_type=options.os_type)
+system.mem_mode = mem_mode
+system.mem_ranges = [AddrRange(start=0x80000000, size=mdesc.mem())]
+
+system.workload = RiscvBareMetal()
+
+system.iobus = IOXBar()
+system.membus = MemBus()
+
+system.system_port = system.membus.slave
+
+system.intrctrl = IntrControl()
+
+# HiFive platform
+system.platform = HiFive()
+
+# CLNT
+system.platform.clint = Clint()
+system.platform.clint.frequency = Frequency("100MHz")
+system.platform.clint.pio = system.membus.master
+
+# PLIC
+system.platform.plic = Plic()
+system.platform.clint.pio_addr = 0x2000000
+system.platform.plic.pio_addr = 0xc000000
+system.platform.plic.n_src = 11
+system.platform.plic.pio = system.membus.master
+
+# UART
+system.uart = Uart8250(pio_addr=0x10000000)
+system.terminal = Terminal()
+system.platform.uart_int_id = 0xa
+system.uart.pio = system.iobus.master
+
+# VirtIOMMIO
+image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False)
+image.child.image_file = mdesc.disks()[0]
+system.platform.disk = MmioVirtIO(
+ vio=VirtIOBlock(image=image),
+ interrupt_id=0x8,
+ pio_size = 4096
+)
+system.platform.disk.pio_addr = 0x10008000
+system.platform.disk.pio = system.iobus.master
+
+# PMA
+system.pma = PMA()
+system.pma.uncacheable = [
+ AddrRange(0x10000000, 0x10000008),
+ AddrRange(0x10008000, 0x10009000),
+ AddrRange(0xc000000, 0xc210000),
+ AddrRange(0x2000000, 0x2010000)
+]
+
+system.bridge = Bridge(delay='50ns')
+system.bridge.master = system.iobus.slave
+system.bridge.slave = system.membus.master
+system.bridge.ranges = [
+ AddrRange(0x10000000, 0x10000080),
+ AddrRange(0x10008000, 0x10009000)
+]
+
+# ---------------------------- Default Setup --------------------------- #
+
+# Set the cache line size for the entire system
+system.cache_line_size = options.cacheline_size
+
+# Create a top-level voltage domain
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
+# Create a source clock for the system and set the clock period
+system.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain
+system.cpu_voltage_domain = VoltageDomain()
+
+# Create a source clock for the CPUs and set the clock period
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ system.cpu_voltage_domain)
+
+system.workload.bootloader = options.kernel
+
+# NOTE: Not yet tested
+if options.script is not None:
+ system.readfile = options.script
+
+system.init_param = options.init_param
+
+system.cpu = [CPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i)
+ for i in range(np)]
+
+if options.caches or options.l2cache:
+ # By default the IOCache runs at the system clock
+ system.iocache = IOCache(addr_ranges = system.mem_ranges)
+ system.iocache.cpu_side = system.iobus.master
+ system.iocache.mem_side = system.membus.slave
+elif not options.external_memory_system:
+ system.iobridge = Bridge(delay='50ns', ranges = system.mem_ranges)
+ system.iobridge.slave = system.iobus.master
+ system.iobridge.master = system.membus.slave
+
+# Sanity check
+if options.simpoint_profile:
+ if not ObjectList.is_noncaching_cpu(CPUClass):
+ fatal("SimPoint generation should be done with atomic cpu")
+ if np > 1:
+ fatal("SimPoint generation not supported with more than one CPUs")
+
+for i in range(np):
+ if options.simpoint_profile:
+ system.cpu[i].addSimPointProbe(options.simpoint_interval)
+ if options.checker:
+ system.cpu[i].addCheckerCpu()
+ if not ObjectList.is_kvm_cpu(CPUClass):
+ if options.bp_type:
+ bpClass = ObjectList.bp_list.get(options.bp_type)
+ system.cpu[i].branchPred = bpClass()
+ if options.indirect_bp_type:
+ IndirectBPClass = ObjectList.indirect_bp_list.get(
+ options.indirect_bp_type)
+ system.cpu[i].branchPred.indirectBranchPred = \
+ IndirectBPClass()
+ system.cpu[i].createThreads()
+
+if options.elastic_trace_en and options.checkpoint_restore == None and \
+ not options.fast_forward:
+ CpuConfig.config_etrace(CPUClass, system.cpu, options)
+
+CacheConfig.config_cache(options, system)
+
+MemConfig.config_mem(options, system)
+
+root = Root(full_system=True, system=system)
+
+Simulation.setWorkCountOptions(system, options)
+Simulation.run(options, root, system, FutureClass)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifd401761be86758340f26edd00a5ab1ca51e6938
Gerrit-Change-Number: 41033
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen <petery....@huawei.com>
Gerrit-MessageType: newchange
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